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gerrit.omnirom.org / android_bionic / 12773b6ecad9970a29b60964b7780b19cb09da9f / . / libc / kernel / uapi / linux / dpll.h
blob: 9b5f37ddc77323c06768f80b350e9feb6ee9caff [file] [log] [blame]
Christopher Ferris0f795212024-01-17 14:17:28 -0800[diff] [blame]1/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
7#ifndef _UAPI_LINUX_DPLL_H
8#define _UAPI_LINUX_DPLL_H
9#define DPLL_FAMILY_NAME "dpll"
10#define DPLL_FAMILY_VERSION 1
11enum dpll_mode {
12 DPLL_MODE_MANUAL = 1,
13 DPLL_MODE_AUTOMATIC,
14 __DPLL_MODE_MAX,
15 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
16};
17enum dpll_lock_status {
18 DPLL_LOCK_STATUS_UNLOCKED = 1,
19 DPLL_LOCK_STATUS_LOCKED,
20 DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
21 DPLL_LOCK_STATUS_HOLDOVER,
22 __DPLL_LOCK_STATUS_MAX,
23 DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)
24};
25#define DPLL_TEMP_DIVIDER 1000
26enum dpll_type {
27 DPLL_TYPE_PPS = 1,
28 DPLL_TYPE_EEC,
29 __DPLL_TYPE_MAX,
30 DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1)
31};
32enum dpll_pin_type {
33 DPLL_PIN_TYPE_MUX = 1,
34 DPLL_PIN_TYPE_EXT,
35 DPLL_PIN_TYPE_SYNCE_ETH_PORT,
36 DPLL_PIN_TYPE_INT_OSCILLATOR,
37 DPLL_PIN_TYPE_GNSS,
38 __DPLL_PIN_TYPE_MAX,
39 DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1)
40};
41enum dpll_pin_direction {
42 DPLL_PIN_DIRECTION_INPUT = 1,
43 DPLL_PIN_DIRECTION_OUTPUT,
44 __DPLL_PIN_DIRECTION_MAX,
45 DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1)
46};
47#define DPLL_PIN_FREQUENCY_1_HZ 1
48#define DPLL_PIN_FREQUENCY_10_KHZ 10000
49#define DPLL_PIN_FREQUENCY_77_5_KHZ 77500
50#define DPLL_PIN_FREQUENCY_10_MHZ 10000000
51enum dpll_pin_state {
52 DPLL_PIN_STATE_CONNECTED = 1,
53 DPLL_PIN_STATE_DISCONNECTED,
54 DPLL_PIN_STATE_SELECTABLE,
55 __DPLL_PIN_STATE_MAX,
56 DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1)
57};
58enum dpll_pin_capabilities {
59 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1,
60 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2,
61 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
62};
63#define DPLL_PHASE_OFFSET_DIVIDER 1000
64enum dpll_a {
65 DPLL_A_ID = 1,
66 DPLL_A_MODULE_NAME,
67 DPLL_A_PAD,
68 DPLL_A_CLOCK_ID,
69 DPLL_A_MODE,
70 DPLL_A_MODE_SUPPORTED,
71 DPLL_A_LOCK_STATUS,
72 DPLL_A_TEMP,
73 DPLL_A_TYPE,
74 __DPLL_A_MAX,
75 DPLL_A_MAX = (__DPLL_A_MAX - 1)
76};
77enum dpll_a_pin {
78 DPLL_A_PIN_ID = 1,
79 DPLL_A_PIN_PARENT_ID,
80 DPLL_A_PIN_MODULE_NAME,
81 DPLL_A_PIN_PAD,
82 DPLL_A_PIN_CLOCK_ID,
83 DPLL_A_PIN_BOARD_LABEL,
84 DPLL_A_PIN_PANEL_LABEL,
85 DPLL_A_PIN_PACKAGE_LABEL,
86 DPLL_A_PIN_TYPE,
87 DPLL_A_PIN_DIRECTION,
88 DPLL_A_PIN_FREQUENCY,
89 DPLL_A_PIN_FREQUENCY_SUPPORTED,
90 DPLL_A_PIN_FREQUENCY_MIN,
91 DPLL_A_PIN_FREQUENCY_MAX,
92 DPLL_A_PIN_PRIO,
93 DPLL_A_PIN_STATE,
94 DPLL_A_PIN_CAPABILITIES,
95 DPLL_A_PIN_PARENT_DEVICE,
96 DPLL_A_PIN_PARENT_PIN,
97 DPLL_A_PIN_PHASE_ADJUST_MIN,
98 DPLL_A_PIN_PHASE_ADJUST_MAX,
99 DPLL_A_PIN_PHASE_ADJUST,
100 DPLL_A_PIN_PHASE_OFFSET,
101 __DPLL_A_PIN_MAX,
102 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
103};
104enum dpll_cmd {
105 DPLL_CMD_DEVICE_ID_GET = 1,
106 DPLL_CMD_DEVICE_GET,
107 DPLL_CMD_DEVICE_SET,
108 DPLL_CMD_DEVICE_CREATE_NTF,
109 DPLL_CMD_DEVICE_DELETE_NTF,
110 DPLL_CMD_DEVICE_CHANGE_NTF,
111 DPLL_CMD_PIN_ID_GET,
112 DPLL_CMD_PIN_GET,
113 DPLL_CMD_PIN_SET,
114 DPLL_CMD_PIN_CREATE_NTF,
115 DPLL_CMD_PIN_DELETE_NTF,
116 DPLL_CMD_PIN_CHANGE_NTF,
117 __DPLL_CMD_MAX,
118 DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1)
119};
120#define DPLL_MCGRP_MONITOR "monitor"
121#endif