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Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Chenga6b53f02013-11-06 15:51:05 -08007#ifndef _UAPI__ASM_ARM_PTRACE_H
8#define _UAPI__ASM_ARM_PTRACE_H
9#include <asm/hwcap.h>
10#define PTRACE_GETREGS 12
Ben Chenga6b53f02013-11-06 15:51:05 -080011#define PTRACE_SETREGS 13
12#define PTRACE_GETFPREGS 14
13#define PTRACE_SETFPREGS 15
14#define PTRACE_GETWMMXREGS 18
Ben Chenga6b53f02013-11-06 15:51:05 -080015#define PTRACE_SETWMMXREGS 19
16#define PTRACE_OLDSETOPTIONS 21
17#define PTRACE_GET_THREAD_AREA 22
18#define PTRACE_SET_SYSCALL 23
Ben Chenga6b53f02013-11-06 15:51:05 -080019#define PTRACE_GETCRUNCHREGS 25
20#define PTRACE_SETCRUNCHREGS 26
21#define PTRACE_GETVFPREGS 27
22#define PTRACE_SETVFPREGS 28
Ben Chenga6b53f02013-11-06 15:51:05 -080023#define PTRACE_GETHBPREGS 29
24#define PTRACE_SETHBPREGS 30
Christopher Ferris934ec942018-01-31 15:29:16 -080025#define PTRACE_GETFDPIC 31
26#define PTRACE_GETFDPIC_EXEC 0
27#define PTRACE_GETFDPIC_INTERP 1
Ben Chenga6b53f02013-11-06 15:51:05 -080028#define USR26_MODE 0x00000000
29#define FIQ26_MODE 0x00000001
Ben Chenga6b53f02013-11-06 15:51:05 -080030#define IRQ26_MODE 0x00000002
31#define SVC26_MODE 0x00000003
32#define USR_MODE 0x00000010
Elliott Hughes8cb52b02013-11-21 13:43:23 -080033#define SVC_MODE 0x00000013
Christopher Ferris38062f92014-07-09 15:33:25 -070034#define FIQ_MODE 0x00000011
35#define IRQ_MODE 0x00000012
Christopher Ferris934ec942018-01-31 15:29:16 -080036#define MON_MODE 0x00000016
Ben Chenga6b53f02013-11-06 15:51:05 -080037#define ABT_MODE 0x00000017
38#define HYP_MODE 0x0000001a
Ben Chenga6b53f02013-11-06 15:51:05 -080039#define UND_MODE 0x0000001b
40#define SYSTEM_MODE 0x0000001f
41#define MODE32_BIT 0x00000010
42#define MODE_MASK 0x0000001f
Christopher Ferris38062f92014-07-09 15:33:25 -070043#define V4_PSR_T_BIT 0x00000020
44#define V7M_PSR_T_BIT 0x01000000
45#define PSR_T_BIT V4_PSR_T_BIT
Ben Chenga6b53f02013-11-06 15:51:05 -080046#define PSR_F_BIT 0x00000040
Ben Chenga6b53f02013-11-06 15:51:05 -080047#define PSR_I_BIT 0x00000080
48#define PSR_A_BIT 0x00000100
49#define PSR_E_BIT 0x00000200
50#define PSR_J_BIT 0x01000000
Ben Chenga6b53f02013-11-06 15:51:05 -080051#define PSR_Q_BIT 0x08000000
52#define PSR_V_BIT 0x10000000
53#define PSR_C_BIT 0x20000000
54#define PSR_Z_BIT 0x40000000
Ben Chenga6b53f02013-11-06 15:51:05 -080055#define PSR_N_BIT 0x80000000
56#define PSR_f 0xff000000
57#define PSR_s 0x00ff0000
58#define PSR_x 0x0000ff00
Ben Chenga6b53f02013-11-06 15:51:05 -080059#define PSR_c 0x000000ff
60#define APSR_MASK 0xf80f0000
61#define PSR_ISET_MASK 0x01000010
62#define PSR_IT_MASK 0x0600fc00
Ben Chenga6b53f02013-11-06 15:51:05 -080063#define PSR_ENDIAN_MASK 0x00000200
64#define PSR_ENDSTATE 0
65#define PT_TEXT_ADDR 0x10000
66#define PT_DATA_ADDR 0x10004
Ben Chenga6b53f02013-11-06 15:51:05 -080067#define PT_TEXT_END_ADDR 0x10008
68#ifndef __ASSEMBLY__
69struct pt_regs {
Tao Baod7db5942015-01-28 10:07:51 -080070 long uregs[18];
Ben Chenga6b53f02013-11-06 15:51:05 -080071};
72#define ARM_cpsr uregs[16]
73#define ARM_pc uregs[15]
74#define ARM_lr uregs[14]
Ben Chenga6b53f02013-11-06 15:51:05 -080075#define ARM_sp uregs[13]
76#define ARM_ip uregs[12]
77#define ARM_fp uregs[11]
78#define ARM_r10 uregs[10]
Ben Chenga6b53f02013-11-06 15:51:05 -080079#define ARM_r9 uregs[9]
80#define ARM_r8 uregs[8]
81#define ARM_r7 uregs[7]
82#define ARM_r6 uregs[6]
Ben Chenga6b53f02013-11-06 15:51:05 -080083#define ARM_r5 uregs[5]
84#define ARM_r4 uregs[4]
85#define ARM_r3 uregs[3]
86#define ARM_r2 uregs[2]
Ben Chenga6b53f02013-11-06 15:51:05 -080087#define ARM_r1 uregs[1]
88#define ARM_r0 uregs[0]
89#define ARM_ORIG_r0 uregs[17]
Tao Baod7db5942015-01-28 10:07:51 -080090#define ARM_VFPREGS_SIZE (32 * 8 + 4)
Christopher Ferris38062f92014-07-09 15:33:25 -070091#endif
92#endif