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gerrit.omnirom.org / android_bionic / 106b3a8a7dc03c19a45e322de425ac56aafac358 / . / libc / kernel / uapi / drm / radeon_drm.h
blob: 5e4c77337f7cb8ff91da959bb762b6e356c3892c [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __RADEON_DRM_H__
20#define __RADEON_DRM_H__
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]21#include "drm.h"
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]22#ifdef __cplusplus
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]24#endif
25#ifndef __RADEON_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]26#define __RADEON_SAREA_DEFINES__
27#define RADEON_UPLOAD_CONTEXT 0x00000001
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29#define RADEON_UPLOAD_VERTFMT 0x00000002
30#define RADEON_UPLOAD_LINE 0x00000004
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]31#define RADEON_UPLOAD_BUMPMAP 0x00000008
32#define RADEON_UPLOAD_MASKS 0x00000010
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34#define RADEON_UPLOAD_VIEWPORT 0x00000020
35#define RADEON_UPLOAD_SETUP 0x00000040
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]36#define RADEON_UPLOAD_TCL 0x00000080
37#define RADEON_UPLOAD_MISC 0x00000100
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39#define RADEON_UPLOAD_TEX0 0x00000200
40#define RADEON_UPLOAD_TEX1 0x00000400
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]41#define RADEON_UPLOAD_TEX2 0x00000800
42#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]44#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
45#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]46#define RADEON_UPLOAD_CLIPRECTS 0x00008000
47#define RADEON_REQUIRE_QUIESCENCE 0x00010000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49#define RADEON_UPLOAD_ZBIAS 0x00020000
50#define RADEON_UPLOAD_ALL 0x003effff
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]51#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
52#define RADEON_EMIT_PP_MISC 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]54#define RADEON_EMIT_PP_CNTL 1
55#define RADEON_EMIT_RB3D_COLORPITCH 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]56#define RADEON_EMIT_RE_LINE_PATTERN 3
57#define RADEON_EMIT_SE_LINE_WIDTH 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]59#define RADEON_EMIT_PP_LUM_MATRIX 5
60#define RADEON_EMIT_PP_ROT_MATRIX_0 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]61#define RADEON_EMIT_RB3D_STENCILREFMASK 7
62#define RADEON_EMIT_SE_VPORT_XSCALE 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64#define RADEON_EMIT_SE_CNTL 9
65#define RADEON_EMIT_SE_CNTL_STATUS 10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]66#define RADEON_EMIT_RE_MISC 11
67#define RADEON_EMIT_PP_TXFILTER_0 12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69#define RADEON_EMIT_PP_BORDER_COLOR_0 13
70#define RADEON_EMIT_PP_TXFILTER_1 14
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]71#define RADEON_EMIT_PP_BORDER_COLOR_1 15
72#define RADEON_EMIT_PP_TXFILTER_2 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74#define RADEON_EMIT_PP_BORDER_COLOR_2 17
75#define RADEON_EMIT_SE_ZBIAS_FACTOR 18
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]76#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19
77#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]79#define R200_EMIT_PP_TXCBLEND_0 21
80#define R200_EMIT_PP_TXCBLEND_1 22
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]81#define R200_EMIT_PP_TXCBLEND_2 23
82#define R200_EMIT_PP_TXCBLEND_3 24
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84#define R200_EMIT_PP_TXCBLEND_4 25
85#define R200_EMIT_PP_TXCBLEND_5 26
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]86#define R200_EMIT_PP_TXCBLEND_6 27
87#define R200_EMIT_PP_TXCBLEND_7 28
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29
90#define R200_EMIT_TFACTOR_0 30
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]91#define R200_EMIT_VTX_FMT_0 31
92#define R200_EMIT_VAP_CTL 32
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94#define R200_EMIT_MATRIX_SELECT_0 33
95#define R200_EMIT_TEX_PROC_CTL_2 34
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]96#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35
97#define R200_EMIT_PP_TXFILTER_0 36
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99#define R200_EMIT_PP_TXFILTER_1 37
100#define R200_EMIT_PP_TXFILTER_2 38
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]101#define R200_EMIT_PP_TXFILTER_3 39
102#define R200_EMIT_PP_TXFILTER_4 40
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]104#define R200_EMIT_PP_TXFILTER_5 41
105#define R200_EMIT_PP_TXOFFSET_0 42
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]106#define R200_EMIT_PP_TXOFFSET_1 43
107#define R200_EMIT_PP_TXOFFSET_2 44
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109#define R200_EMIT_PP_TXOFFSET_3 45
110#define R200_EMIT_PP_TXOFFSET_4 46
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]111#define R200_EMIT_PP_TXOFFSET_5 47
112#define R200_EMIT_VTE_CNTL 48
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]114#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49
115#define R200_EMIT_PP_TAM_DEBUG3 50
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]116#define R200_EMIT_PP_CNTL_X 51
117#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53
120#define R200_EMIT_RE_SCISSOR_TL_0 54
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]121#define R200_EMIT_RE_SCISSOR_TL_1 55
122#define R200_EMIT_RE_SCISSOR_TL_2 56
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124#define R200_EMIT_SE_VAP_CNTL_STATUS 57
125#define R200_EMIT_SE_VTX_STATE_CNTL 58
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]126#define R200_EMIT_RE_POINTSIZE 59
127#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129#define R200_EMIT_PP_CUBIC_FACES_0 61
130#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]131#define R200_EMIT_PP_CUBIC_FACES_1 63
132#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134#define R200_EMIT_PP_CUBIC_FACES_2 65
135#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]136#define R200_EMIT_PP_CUBIC_FACES_3 67
137#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139#define R200_EMIT_PP_CUBIC_FACES_4 69
140#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]141#define R200_EMIT_PP_CUBIC_FACES_5 71
142#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144#define RADEON_EMIT_PP_TEX_SIZE_0 73
145#define RADEON_EMIT_PP_TEX_SIZE_1 74
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]146#define RADEON_EMIT_PP_TEX_SIZE_2 75
147#define R200_EMIT_RB3D_BLENDCOLOR 76
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
150#define RADEON_EMIT_PP_CUBIC_FACES_0 78
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]151#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
152#define RADEON_EMIT_PP_CUBIC_FACES_1 80
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
155#define RADEON_EMIT_PP_CUBIC_FACES_2 82
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]156#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
157#define R200_EMIT_PP_TRI_PERF_CNTL 84
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]159#define R200_EMIT_PP_AFS_0 85
160#define R200_EMIT_PP_AFS_1 86
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]161#define R200_EMIT_ATF_TFACTOR 87
162#define R200_EMIT_PP_TXCTLALL_0 88
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]164#define R200_EMIT_PP_TXCTLALL_1 89
165#define R200_EMIT_PP_TXCTLALL_2 90
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]166#define R200_EMIT_PP_TXCTLALL_3 91
167#define R200_EMIT_PP_TXCTLALL_4 92
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]169#define R200_EMIT_PP_TXCTLALL_5 93
170#define R200_EMIT_VAP_PVS_CNTL 94
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]171#define RADEON_MAX_STATE_PACKETS 95
172#define RADEON_CMD_PACKET 1
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174#define RADEON_CMD_SCALARS 2
175#define RADEON_CMD_VECTORS 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]176#define RADEON_CMD_DMA_DISCARD 4
177#define RADEON_CMD_PACKET3 5
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179#define RADEON_CMD_PACKET3_CLIP 6
180#define RADEON_CMD_SCALARS2 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]181#define RADEON_CMD_WAIT 8
182#define RADEON_CMD_VECLINEAR 9
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184typedef union {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]185 int i;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]186 struct {
187 unsigned char cmd_type, pad0, pad1, pad2;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]189 } header;
190 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]191 unsigned char cmd_type, packet_id, pad0, pad1;
192 } packet;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]194 struct {
195 unsigned char cmd_type, offset, stride, count;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]196 } scalars;
197 struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]199 unsigned char cmd_type, offset, stride, count;
200 } vectors;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]201 struct {
202 unsigned char cmd_type, addr_lo, addr_hi, count;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]204 } veclinear;
205 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]206 unsigned char cmd_type, buf_idx, pad0, pad1;
207 } dma;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]209 struct {
210 unsigned char cmd_type, flags, pad0, pad1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]211 } wait;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]212} drm_radeon_cmd_header_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214#define RADEON_WAIT_2D 0x1
215#define RADEON_WAIT_3D 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]216#define R300_CMD_PACKET3_CLEAR 0
217#define R300_CMD_PACKET3_RAW 1
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define R300_CMD_PACKET0 1
220#define R300_CMD_VPU 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]221#define R300_CMD_PACKET3 3
222#define R300_CMD_END3D 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224#define R300_CMD_CP_DELAY 5
225#define R300_CMD_DMA_DISCARD 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]226#define R300_CMD_WAIT 7
227#define R300_WAIT_2D 0x1
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]229#define R300_WAIT_3D 0x2
230#define R300_WAIT_2D_CLEAN 0x3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]231#define R300_WAIT_3D_CLEAN 0x4
232#define R300_NEW_WAIT_2D_3D 0x3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]234#define R300_NEW_WAIT_2D_2D_CLEAN 0x4
235#define R300_NEW_WAIT_3D_3D_CLEAN 0x6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]236#define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
237#define R300_CMD_SCRATCH 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]239#define R300_CMD_R500FP 9
240typedef union {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]241 unsigned int u;
242 struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]244 unsigned char cmd_type, pad0, pad1, pad2;
245 } header;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]246 struct {
247 unsigned char cmd_type, count, reglo, reghi;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]249 } packet0;
250 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]251 unsigned char cmd_type, count, adrlo, adrhi;
252 } vpu;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]254 struct {
255 unsigned char cmd_type, packet, pad0, pad1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]256 } packet3;
257 struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]259 unsigned char cmd_type, packet;
260 unsigned short count;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]261 } delay;
262 struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]264 unsigned char cmd_type, buf_idx, pad0, pad1;
265 } dma;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]266 struct {
267 unsigned char cmd_type, flags, pad0, pad1;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]269 } wait;
270 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]271 unsigned char cmd_type, reg, n_bufs, flags;
272 } scratch;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]274 struct {
275 unsigned char cmd_type, count, adrlo, adrhi_flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]276 } r500fp;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]277} drm_r300_cmd_header_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]279#define RADEON_FRONT 0x1
280#define RADEON_BACK 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]281#define RADEON_DEPTH 0x4
282#define RADEON_STENCIL 0x8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]284#define RADEON_CLEAR_FASTZ 0x80000000
285#define RADEON_USE_HIERZ 0x40000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]286#define RADEON_USE_COMP_ZBUF 0x20000000
287#define R500FP_CONSTANT_TYPE (1 << 1)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]289#define R500FP_CONSTANT_CLAMP (1 << 2)
290#define RADEON_POINTS 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]291#define RADEON_LINES 0x2
292#define RADEON_LINE_STRIP 0x3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]294#define RADEON_TRIANGLES 0x4
295#define RADEON_TRIANGLE_FAN 0x5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]296#define RADEON_TRIANGLE_STRIP 0x6
297#define RADEON_BUFFER_SIZE 65536
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]299#define RADEON_INDEX_PRIM_OFFSET 20
300#define RADEON_SCRATCH_REG_OFFSET 32
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]301#define R600_SCRATCH_REG_OFFSET 256
302#define RADEON_NR_SAREA_CLIPRECTS 12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]304#define RADEON_LOCAL_TEX_HEAP 0
305#define RADEON_GART_TEX_HEAP 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]306#define RADEON_NR_TEX_HEAPS 2
307#define RADEON_NR_TEX_REGIONS 64
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]309#define RADEON_LOG_TEX_GRANULARITY 16
310#define RADEON_MAX_TEXTURE_LEVELS 12
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]311#define RADEON_MAX_TEXTURE_UNITS 3
312#define RADEON_MAX_SURFACES 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]314#define RADEON_OFFSET_SHIFT 10
315#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]316#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
317#endif
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]319typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]320 unsigned int red;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]321 unsigned int green;
322 unsigned int blue;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]324 unsigned int alpha;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]325} radeon_color_regs_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]326typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]327 unsigned int pp_misc;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]329 unsigned int pp_fog_color;
330 unsigned int re_solid_color;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]331 unsigned int rb3d_blendcntl;
332 unsigned int rb3d_depthoffset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]334 unsigned int rb3d_depthpitch;
335 unsigned int rb3d_zstencilcntl;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]336 unsigned int pp_cntl;
337 unsigned int rb3d_cntl;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]339 unsigned int rb3d_coloroffset;
340 unsigned int re_width_height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]341 unsigned int rb3d_colorpitch;
342 unsigned int se_cntl;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]344 unsigned int se_coord_fmt;
345 unsigned int re_line_pattern;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]346 unsigned int re_line_state;
347 unsigned int se_line_width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]349 unsigned int pp_lum_matrix;
350 unsigned int pp_rot_matrix_0;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]351 unsigned int pp_rot_matrix_1;
352 unsigned int rb3d_stencilrefmask;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]354 unsigned int rb3d_ropcntl;
355 unsigned int rb3d_planemask;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]356 unsigned int se_vport_xscale;
357 unsigned int se_vport_xoffset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]359 unsigned int se_vport_yscale;
360 unsigned int se_vport_yoffset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]361 unsigned int se_vport_zscale;
362 unsigned int se_vport_zoffset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]364 unsigned int se_cntl_status;
365 unsigned int re_top_left;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]366 unsigned int re_misc;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]367} drm_radeon_context_regs_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]369typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]370 unsigned int se_zbias_factor;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]371 unsigned int se_zbias_constant;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]372} drm_radeon_context2_regs_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]374typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]375 unsigned int pp_txfilter;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]376 unsigned int pp_txformat;
377 unsigned int pp_txoffset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]379 unsigned int pp_txcblend;
380 unsigned int pp_txablend;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]381 unsigned int pp_tfactor;
382 unsigned int pp_border_color;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]384} drm_radeon_texture_regs_t;
385typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]386 unsigned int start;
387 unsigned int finish;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]389 unsigned int prim : 8;
390 unsigned int stateidx : 8;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]391 unsigned int numverts : 16;
392 unsigned int vc_format;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]394} drm_radeon_prim_t;
395typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]396 drm_radeon_context_regs_t context;
397 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]399 drm_radeon_context2_regs_t context2;
400 unsigned int dirty;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]401} drm_radeon_state_t;
402typedef struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]404 drm_radeon_context_regs_t context_state;
405 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]406 unsigned int dirty;
407 unsigned int vertsize;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]409 unsigned int vc_format;
410 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]411 unsigned int nbox;
412 unsigned int last_frame;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]414 unsigned int last_dispatch;
415 unsigned int last_clear;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]416 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1];
417 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]419 int ctx_owner;
420 int pfState;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]421 int pfCurrentPage;
422 int crtc2_base;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]424 int tiling_enabled;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]425} drm_radeon_sarea_t;
426#define DRM_RADEON_CP_INIT 0x00
427#define DRM_RADEON_CP_START 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]429#define DRM_RADEON_CP_STOP 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]430#define DRM_RADEON_CP_RESET 0x03
431#define DRM_RADEON_CP_IDLE 0x04
432#define DRM_RADEON_RESET 0x05
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]434#define DRM_RADEON_FULLSCREEN 0x06
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]435#define DRM_RADEON_SWAP 0x07
436#define DRM_RADEON_CLEAR 0x08
437#define DRM_RADEON_VERTEX 0x09
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]439#define DRM_RADEON_INDICES 0x0A
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]440#define DRM_RADEON_NOT_USED
441#define DRM_RADEON_STIPPLE 0x0C
442#define DRM_RADEON_INDIRECT 0x0D
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]444#define DRM_RADEON_TEXTURE 0x0E
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]445#define DRM_RADEON_VERTEX2 0x0F
446#define DRM_RADEON_CMDBUF 0x10
447#define DRM_RADEON_GETPARAM 0x11
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]449#define DRM_RADEON_FLIP 0x12
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]450#define DRM_RADEON_ALLOC 0x13
451#define DRM_RADEON_FREE 0x14
452#define DRM_RADEON_INIT_HEAP 0x15
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]454#define DRM_RADEON_IRQ_EMIT 0x16
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]455#define DRM_RADEON_IRQ_WAIT 0x17
456#define DRM_RADEON_CP_RESUME 0x18
457#define DRM_RADEON_SETPARAM 0x19
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]459#define DRM_RADEON_SURF_ALLOC 0x1a
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]460#define DRM_RADEON_SURF_FREE 0x1b
461#define DRM_RADEON_GEM_INFO 0x1c
462#define DRM_RADEON_GEM_CREATE 0x1d
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]464#define DRM_RADEON_GEM_MMAP 0x1e
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]465#define DRM_RADEON_GEM_PREAD 0x21
466#define DRM_RADEON_GEM_PWRITE 0x22
467#define DRM_RADEON_GEM_SET_DOMAIN 0x23
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]469#define DRM_RADEON_GEM_WAIT_IDLE 0x24
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]470#define DRM_RADEON_CS 0x26
471#define DRM_RADEON_INFO 0x27
472#define DRM_RADEON_GEM_SET_TILING 0x28
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]474#define DRM_RADEON_GEM_GET_TILING 0x29
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]475#define DRM_RADEON_GEM_BUSY 0x2a
476#define DRM_RADEON_GEM_VA 0x2b
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]477#define DRM_RADEON_GEM_OP 0x2c
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]479#define DRM_RADEON_GEM_USERPTR 0x2d
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]480#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]481#define DRM_IOCTL_RADEON_CP_START DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START)
482#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]484#define DRM_IOCTL_RADEON_CP_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
485#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]486#define DRM_IOCTL_RADEON_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET)
487#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]489#define DRM_IOCTL_RADEON_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP)
490#define DRM_IOCTL_RADEON_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]491#define DRM_IOCTL_RADEON_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
492#define DRM_IOCTL_RADEON_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]494#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]495#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]496#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]497#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]499#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]500#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]501#define DRM_IOCTL_RADEON_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]502#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]504#define DRM_IOCTL_RADEON_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
505#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]506#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]507#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]508/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]509#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
510#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]511#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
512#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]513/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]514#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]515#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]516#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]517#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]518/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]519#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]520#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]521#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]522#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]523/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]524#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]525#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]526#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]527#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]528/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]529#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]530#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
531#define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]532typedef struct drm_radeon_init {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]533/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]534 enum {
535 RADEON_INIT_CP = 0x01,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]536 RADEON_CLEANUP_CP = 0x02,
537 RADEON_INIT_R200_CP = 0x03,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]538/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]539 RADEON_INIT_R300_CP = 0x04,
540 RADEON_INIT_R600_CP = 0x05
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]541 } func;
542 unsigned long sarea_priv_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]543/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]544 int is_pci;
545 int cp_mode;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]546 int gart_size;
547 int ring_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]548/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]549 int usec_timeout;
550 unsigned int fb_bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]551 unsigned int front_offset, front_pitch;
552 unsigned int back_offset, back_pitch;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]553/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]554 unsigned int depth_bpp;
555 unsigned int depth_offset, depth_pitch;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]556 unsigned long fb_offset;
557 unsigned long mmio_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]558/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]559 unsigned long ring_offset;
560 unsigned long ring_rptr_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]561 unsigned long buffers_offset;
562 unsigned long gart_textures_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]563/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]564} drm_radeon_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]565typedef struct drm_radeon_cp_stop {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]566 int flush;
567 int idle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]568/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]569} drm_radeon_cp_stop_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]570typedef struct drm_radeon_fullscreen {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]571 enum {
572 RADEON_INIT_FULLSCREEN = 0x01,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]573/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]574 RADEON_CLEANUP_FULLSCREEN = 0x02
575 } func;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]576} drm_radeon_fullscreen_t;
577#define CLEAR_X1 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]578/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]579#define CLEAR_Y1 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]580#define CLEAR_X2 2
581#define CLEAR_Y2 3
582#define CLEAR_DEPTH 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]583/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]584typedef union drm_radeon_clear_rect {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]585 float f[5];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]586 unsigned int ui[5];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]587} drm_radeon_clear_rect_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]588/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]589typedef struct drm_radeon_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]590 unsigned int flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]591 unsigned int clear_color;
592 unsigned int clear_depth;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]593/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]594 unsigned int color_mask;
595 unsigned int depth_mask;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]596 drm_radeon_clear_rect_t __user * depth_boxes;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]597} drm_radeon_clear_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]598/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]599typedef struct drm_radeon_vertex {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]600 int prim;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]601 int idx;
602 int count;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]603/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]604 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]605} drm_radeon_vertex_t;
606typedef struct drm_radeon_indices {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]607 int prim;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]608/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]609 int idx;
610 int start;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]611 int end;
612 int discard;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]613/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]614} drm_radeon_indices_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]615typedef struct drm_radeon_vertex2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]616 int idx;
617 int discard;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]618/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]619 int nr_states;
620 drm_radeon_state_t __user * state;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]621 int nr_prims;
622 drm_radeon_prim_t __user * prim;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]623/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]624} drm_radeon_vertex2_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]625typedef struct drm_radeon_cmd_buffer {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]626 int bufsz;
627 char __user * buf;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]628/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]629 int nbox;
630 struct drm_clip_rect __user * boxes;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]631} drm_radeon_cmd_buffer_t;
632typedef struct drm_radeon_tex_image {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]633/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]634 unsigned int x, y;
635 unsigned int width, height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]636 const void __user * data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]637} drm_radeon_tex_image_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]638/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]639typedef struct drm_radeon_texture {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]640 unsigned int offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]641 int pitch;
642 int format;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]643/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]644 int width;
645 int height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]646 drm_radeon_tex_image_t __user * image;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]647} drm_radeon_texture_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]648/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]649typedef struct drm_radeon_stipple {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]650 unsigned int __user * mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]651} drm_radeon_stipple_t;
652typedef struct drm_radeon_indirect {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]653/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]654 int idx;
655 int start;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]656 int end;
657 int discard;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]658/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]659} drm_radeon_indirect_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]660#define RADEON_CARD_PCI 0
661#define RADEON_CARD_AGP 1
662#define RADEON_CARD_PCIE 2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]663/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]664#define RADEON_PARAM_GART_BUFFER_OFFSET 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]665#define RADEON_PARAM_LAST_FRAME 2
666#define RADEON_PARAM_LAST_DISPATCH 3
667#define RADEON_PARAM_LAST_CLEAR 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]668/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]669#define RADEON_PARAM_IRQ_NR 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]670#define RADEON_PARAM_GART_BASE 6
671#define RADEON_PARAM_REGISTER_HANDLE 7
672#define RADEON_PARAM_STATUS_HANDLE 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]673/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]674#define RADEON_PARAM_SAREA_HANDLE 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]675#define RADEON_PARAM_GART_TEX_HANDLE 10
676#define RADEON_PARAM_SCRATCH_OFFSET 11
677#define RADEON_PARAM_CARD_TYPE 12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]678/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]679#define RADEON_PARAM_VBLANK_CRTC 13
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]680#define RADEON_PARAM_FB_LOCATION 14
681#define RADEON_PARAM_NUM_GB_PIPES 15
682#define RADEON_PARAM_DEVICE_ID 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]683/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]684#define RADEON_PARAM_NUM_Z_PIPES 17
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]685typedef struct drm_radeon_getparam {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]686 int param;
687 void __user * value;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]688/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]689} drm_radeon_getparam_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]690#define RADEON_MEM_REGION_GART 1
691#define RADEON_MEM_REGION_FB 2
692typedef struct drm_radeon_mem_alloc {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]693/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]694 int region;
695 int alignment;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]696 int size;
697 int __user * region_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]698/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]699} drm_radeon_mem_alloc_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]700typedef struct drm_radeon_mem_free {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]701 int region;
702 int region_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]703/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]704} drm_radeon_mem_free_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]705typedef struct drm_radeon_mem_init_heap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]706 int region;
707 int size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]708/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]709 int start;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]710} drm_radeon_mem_init_heap_t;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]711typedef struct drm_radeon_irq_emit {
712 int __user * irq_seq;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]713/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]714} drm_radeon_irq_emit_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]715typedef struct drm_radeon_irq_wait {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]716 int irq_seq;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]717} drm_radeon_irq_wait_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]718/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]719typedef struct drm_radeon_setparam {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]720 unsigned int param;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]721 __s64 value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]722} drm_radeon_setparam_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]723/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]724#define RADEON_SETPARAM_FB_LOCATION 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]725#define RADEON_SETPARAM_SWITCH_TILING 2
726#define RADEON_SETPARAM_PCIGART_LOCATION 3
727#define RADEON_SETPARAM_NEW_MEMMAP 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]728/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]729#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]730#define RADEON_SETPARAM_VBLANK_CRTC 6
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]731typedef struct drm_radeon_surface_alloc {
732 unsigned int address;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]733/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]734 unsigned int size;
735 unsigned int flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]736} drm_radeon_surface_alloc_t;
737typedef struct drm_radeon_surface_free {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]738/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]739 unsigned int address;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]740} drm_radeon_surface_free_t;
741#define DRM_RADEON_VBLANK_CRTC1 1
742#define DRM_RADEON_VBLANK_CRTC2 2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]743/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]744#define RADEON_GEM_DOMAIN_CPU 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]745#define RADEON_GEM_DOMAIN_GTT 0x2
746#define RADEON_GEM_DOMAIN_VRAM 0x4
747struct drm_radeon_gem_info {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]748/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]749 __u64 gart_size;
750 __u64 vram_size;
751 __u64 vram_visible;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]752};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]753/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]754#define RADEON_GEM_NO_BACKING_STORE (1 << 0)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]755#define RADEON_GEM_GTT_UC (1 << 1)
756#define RADEON_GEM_GTT_WC (1 << 2)
757#define RADEON_GEM_CPU_ACCESS (1 << 3)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]758/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]759#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]760struct drm_radeon_gem_create {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]761 __u64 size;
762 __u64 alignment;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]763/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]764 __u32 handle;
765 __u32 initial_domain;
766 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]767};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]768/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]769#define RADEON_GEM_USERPTR_READONLY (1 << 0)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]770#define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
771#define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
772#define RADEON_GEM_USERPTR_REGISTER (1 << 3)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]773/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]774struct drm_radeon_gem_userptr {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]775 __u64 addr;
776 __u64 size;
777 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]778/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]779 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]780};
781#define RADEON_TILING_MACRO 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]782#define RADEON_TILING_MICRO 0x2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]783/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]784#define RADEON_TILING_SWAP_16BIT 0x4
785#define RADEON_TILING_SWAP_32BIT 0x8
786#define RADEON_TILING_SURFACE 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]787#define RADEON_TILING_MICRO_SQUARE 0x20
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]788/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]789#define RADEON_TILING_EG_BANKW_SHIFT 8
790#define RADEON_TILING_EG_BANKW_MASK 0xf
791#define RADEON_TILING_EG_BANKH_SHIFT 12
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]792#define RADEON_TILING_EG_BANKH_MASK 0xf
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]793/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]794#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
795#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
796#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]797#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]798/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]799#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
800#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]801struct drm_radeon_gem_set_tiling {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]802 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]803/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]804 __u32 tiling_flags;
805 __u32 pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]806};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]807struct drm_radeon_gem_get_tiling {
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]808/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]809 __u32 handle;
810 __u32 tiling_flags;
811 __u32 pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]812};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]813/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]814struct drm_radeon_gem_mmap {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]815 __u32 handle;
816 __u32 pad;
817 __u64 offset;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]818/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]819 __u64 size;
820 __u64 addr_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]821};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]822struct drm_radeon_gem_set_domain {
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]823/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]824 __u32 handle;
825 __u32 read_domains;
826 __u32 write_domain;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]827};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]828/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]829struct drm_radeon_gem_wait_idle {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]830 __u32 handle;
831 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]832};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]833/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]834struct drm_radeon_gem_busy {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]835 __u32 handle;
836 __u32 domain;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]837};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]838/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]839struct drm_radeon_gem_pread {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]840 __u32 handle;
841 __u32 pad;
842 __u64 offset;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]843/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]844 __u64 size;
845 __u64 data_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]846};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]847struct drm_radeon_gem_pwrite {
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]848/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]849 __u32 handle;
850 __u32 pad;
851 __u64 offset;
852 __u64 size;
853/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
854 __u64 data_ptr;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]855};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]856struct drm_radeon_gem_op {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]857 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]858/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]859 __u32 op;
860 __u64 value;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]861};
862#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]863/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]864#define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]865#define RADEON_VA_MAP 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]866#define RADEON_VA_UNMAP 2
867#define RADEON_VA_RESULT_OK 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]868/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]869#define RADEON_VA_RESULT_ERROR 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]870#define RADEON_VA_RESULT_VA_EXIST 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]871#define RADEON_VM_PAGE_VALID (1 << 0)
872#define RADEON_VM_PAGE_READABLE (1 << 1)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]873/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]874#define RADEON_VM_PAGE_WRITEABLE (1 << 2)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]875#define RADEON_VM_PAGE_SYSTEM (1 << 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]876#define RADEON_VM_PAGE_SNOOPED (1 << 4)
877struct drm_radeon_gem_va {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]878/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]879 __u32 handle;
880 __u32 operation;
881 __u32 vm_id;
882 __u32 flags;
883/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
884 __u64 offset;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]885};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]886#define RADEON_CHUNK_ID_RELOCS 0x01
887#define RADEON_CHUNK_ID_IB 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]888/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]889#define RADEON_CHUNK_ID_FLAGS 0x03
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]890#define RADEON_CHUNK_ID_CONST_IB 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]891#define RADEON_CS_KEEP_TILING_FLAGS 0x01
892#define RADEON_CS_USE_VM 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]893/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]894#define RADEON_CS_END_OF_FRAME 0x04
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]895#define RADEON_CS_RING_GFX 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]896#define RADEON_CS_RING_COMPUTE 1
897#define RADEON_CS_RING_DMA 2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]898/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]899#define RADEON_CS_RING_UVD 3
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]900#define RADEON_CS_RING_VCE 4
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]901struct drm_radeon_cs_chunk {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]902 __u32 chunk_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]903/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]904 __u32 length_dw;
905 __u64 chunk_data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]906};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]907#define RADEON_RELOC_PRIO_MASK (0xf << 0)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]908/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]909struct drm_radeon_cs_reloc {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]910 __u32 handle;
911 __u32 read_domains;
912 __u32 write_domain;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]913/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]914 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]915};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]916struct drm_radeon_cs {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]917 __u32 num_chunks;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]918/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]919 __u32 cs_id;
920 __u64 chunks;
921 __u64 gart_limit;
922 __u64 vram_limit;
923/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]924};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]925#define RADEON_INFO_DEVICE_ID 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]926#define RADEON_INFO_NUM_GB_PIPES 0x01
927#define RADEON_INFO_NUM_Z_PIPES 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]928/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]929#define RADEON_INFO_ACCEL_WORKING 0x03
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]930#define RADEON_INFO_CRTC_FROM_ID 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]931#define RADEON_INFO_ACCEL_WORKING2 0x05
932#define RADEON_INFO_TILING_CONFIG 0x06
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]933/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]934#define RADEON_INFO_WANT_HYPERZ 0x07
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]935#define RADEON_INFO_WANT_CMASK 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]936#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09
937#define RADEON_INFO_NUM_BACKENDS 0x0a
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]938/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]939#define RADEON_INFO_NUM_TILE_PIPES 0x0b
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]940#define RADEON_INFO_FUSION_GART_WORKING 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]941#define RADEON_INFO_BACKEND_MAP 0x0d
942#define RADEON_INFO_VA_START 0x0e
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]943/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]944#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]945#define RADEON_INFO_MAX_PIPES 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]946#define RADEON_INFO_TIMESTAMP 0x11
947#define RADEON_INFO_MAX_SE 0x12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]948/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]949#define RADEON_INFO_MAX_SH_PER_SE 0x13
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]950#define RADEON_INFO_FASTFB_WORKING 0x14
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]951#define RADEON_INFO_RING_WORKING 0x15
952#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]953/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]954#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]955#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]956#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
957#define RADEON_INFO_MAX_SCLK 0x1a
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]958/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]959#define RADEON_INFO_VCE_FW_VERSION 0x1b
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]960#define RADEON_INFO_VCE_FB_VERSION 0x1c
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]961#define RADEON_INFO_NUM_BYTES_MOVED 0x1d
962#define RADEON_INFO_VRAM_USAGE 0x1e
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]963/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]964#define RADEON_INFO_GTT_USAGE 0x1f
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]965#define RADEON_INFO_ACTIVE_CU_COUNT 0x20
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]966#define RADEON_INFO_CURRENT_GPU_TEMP 0x21
967#define RADEON_INFO_CURRENT_GPU_SCLK 0x22
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]968/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]969#define RADEON_INFO_CURRENT_GPU_MCLK 0x23
970#define RADEON_INFO_READ_REG 0x24
Christopher Ferrisdda4fd42015-07-13 17:21:18 -0700[diff] [blame]971#define RADEON_INFO_VA_UNMAP_WORKING 0x25
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]972#define RADEON_INFO_GPU_RESET_COUNTER 0x26
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]973/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]974struct drm_radeon_info {
975 __u32 request;
976 __u32 pad;
977 __u64 value;
978/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]979};
980#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]981#define SI_TILE_MODE_COLOR_1D 13
Christopher Ferrisdda4fd42015-07-13 17:21:18 -0700[diff] [blame]982#define SI_TILE_MODE_COLOR_1D_SCANOUT 9
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]983/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]984#define SI_TILE_MODE_COLOR_2D_8BPP 14
985#define SI_TILE_MODE_COLOR_2D_16BPP 15
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]986#define SI_TILE_MODE_COLOR_2D_32BPP 16
Christopher Ferrisdda4fd42015-07-13 17:21:18 -0700[diff] [blame]987#define SI_TILE_MODE_COLOR_2D_64BPP 17
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]988/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]989#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
990#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]991#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
Christopher Ferrisdda4fd42015-07-13 17:21:18 -0700[diff] [blame]992#define SI_TILE_MODE_DEPTH_STENCIL_2D 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]993/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]994#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
995#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]996#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
Christopher Ferrisdda4fd42015-07-13 17:21:18 -0700[diff] [blame]997#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]998/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
999#ifdef __cplusplus
1000#endif
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]1001#endif