blob: 18346587217d23a5a42ff46024d1b44d115baa09 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef OMAP3_ISP_USER_H
20#define OMAP3_ISP_USER_H
21#include <linux/types.h>
22#include <linux/videodev2.h>
Tao Baod7db5942015-01-28 10:07:51 -080023#define VIDIOC_OMAP3ISP_CCDC_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct omap3isp_ccdc_update_config)
24#define VIDIOC_OMAP3ISP_PRV_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct omap3isp_prev_update_config)
25#define VIDIOC_OMAP3ISP_AEWB_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct omap3isp_h3a_aewb_config)
26#define VIDIOC_OMAP3ISP_HIST_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct omap3isp_hist_config)
Tao Baod7db5942015-01-28 10:07:51 -080027#define VIDIOC_OMAP3ISP_AF_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct omap3isp_h3a_af_config)
28#define VIDIOC_OMAP3ISP_STAT_REQ _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct omap3isp_stat_data)
Christopher Ferris9ce28842018-10-25 12:11:39 -070029#define VIDIOC_OMAP3ISP_STAT_REQ_TIME32 _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct omap3isp_stat_data_time32)
Tao Baod7db5942015-01-28 10:07:51 -080030#define VIDIOC_OMAP3ISP_STAT_EN _IOWR('V', BASE_VIDIOC_PRIVATE + 7, unsigned long)
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define V4L2_EVENT_OMAP3ISP_CLASS (V4L2_EVENT_PRIVATE_START | 0x100)
Ben Cheng655a7c02013-10-16 16:09:24 -070032#define V4L2_EVENT_OMAP3ISP_AEWB (V4L2_EVENT_OMAP3ISP_CLASS | 0x1)
33#define V4L2_EVENT_OMAP3ISP_AF (V4L2_EVENT_OMAP3ISP_CLASS | 0x2)
34#define V4L2_EVENT_OMAP3ISP_HIST (V4L2_EVENT_OMAP3ISP_CLASS | 0x3)
35struct omap3isp_stat_event_status {
Tao Baod7db5942015-01-28 10:07:51 -080036 __u32 frame_number;
37 __u16 config_counter;
38 __u8 buf_err;
Ben Cheng655a7c02013-10-16 16:09:24 -070039};
Ben Cheng655a7c02013-10-16 16:09:24 -070040#define OMAP3ISP_AEWB_MAX_SATURATION_LIM 1023
41#define OMAP3ISP_AEWB_MIN_WIN_H 2
42#define OMAP3ISP_AEWB_MAX_WIN_H 256
43#define OMAP3ISP_AEWB_MIN_WIN_W 6
Ben Cheng655a7c02013-10-16 16:09:24 -070044#define OMAP3ISP_AEWB_MAX_WIN_W 256
45#define OMAP3ISP_AEWB_MIN_WINVC 1
46#define OMAP3ISP_AEWB_MIN_WINHC 1
47#define OMAP3ISP_AEWB_MAX_WINVC 128
Ben Cheng655a7c02013-10-16 16:09:24 -070048#define OMAP3ISP_AEWB_MAX_WINHC 36
49#define OMAP3ISP_AEWB_MAX_WINSTART 4095
50#define OMAP3ISP_AEWB_MIN_SUB_INC 2
51#define OMAP3ISP_AEWB_MAX_SUB_INC 32
Ben Cheng655a7c02013-10-16 16:09:24 -070052#define OMAP3ISP_AEWB_MAX_BUF_SIZE 83600
53#define OMAP3ISP_AF_IIRSH_MIN 0
54#define OMAP3ISP_AF_IIRSH_MAX 4095
55#define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MIN 1
Ben Cheng655a7c02013-10-16 16:09:24 -070056#define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MAX 36
57#define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MIN 1
58#define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MAX 128
59#define OMAP3ISP_AF_PAXEL_INCREMENT_MIN 2
Ben Cheng655a7c02013-10-16 16:09:24 -070060#define OMAP3ISP_AF_PAXEL_INCREMENT_MAX 32
61#define OMAP3ISP_AF_PAXEL_HEIGHT_MIN 2
62#define OMAP3ISP_AF_PAXEL_HEIGHT_MAX 256
63#define OMAP3ISP_AF_PAXEL_WIDTH_MIN 16
Ben Cheng655a7c02013-10-16 16:09:24 -070064#define OMAP3ISP_AF_PAXEL_WIDTH_MAX 256
65#define OMAP3ISP_AF_PAXEL_HZSTART_MIN 1
66#define OMAP3ISP_AF_PAXEL_HZSTART_MAX 4095
67#define OMAP3ISP_AF_PAXEL_VTSTART_MIN 0
Ben Cheng655a7c02013-10-16 16:09:24 -070068#define OMAP3ISP_AF_PAXEL_VTSTART_MAX 4095
69#define OMAP3ISP_AF_THRESHOLD_MAX 255
70#define OMAP3ISP_AF_COEF_MAX 4095
71#define OMAP3ISP_AF_PAXEL_SIZE 48
Ben Cheng655a7c02013-10-16 16:09:24 -070072#define OMAP3ISP_AF_MAX_BUF_SIZE 221184
73struct omap3isp_h3a_aewb_config {
Tao Baod7db5942015-01-28 10:07:51 -080074 __u32 buf_size;
75 __u16 config_counter;
Tao Baod7db5942015-01-28 10:07:51 -080076 __u16 saturation_limit;
77 __u16 win_height;
78 __u16 win_width;
79 __u16 ver_win_count;
Tao Baod7db5942015-01-28 10:07:51 -080080 __u16 hor_win_count;
81 __u16 ver_win_start;
82 __u16 hor_win_start;
83 __u16 blk_ver_win_start;
Tao Baod7db5942015-01-28 10:07:51 -080084 __u16 blk_win_height;
85 __u16 subsample_ver_inc;
86 __u16 subsample_hor_inc;
87 __u8 alaw_enable;
Ben Cheng655a7c02013-10-16 16:09:24 -070088};
89struct omap3isp_stat_data {
Tao Baod7db5942015-01-28 10:07:51 -080090 struct timeval ts;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -070091 void * buf;
Christopher Ferris10a76e62022-06-08 13:31:52 -070092 __struct_group(, frame,, __u32 buf_size;
Tao Baod7db5942015-01-28 10:07:51 -080093 __u16 frame_number;
94 __u16 cur_frame;
95 __u16 config_counter;
Christopher Ferris10a76e62022-06-08 13:31:52 -070096 );
Ben Cheng655a7c02013-10-16 16:09:24 -070097};
98#define OMAP3ISP_HIST_BINS_32 0
99#define OMAP3ISP_HIST_BINS_64 1
100#define OMAP3ISP_HIST_BINS_128 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700101#define OMAP3ISP_HIST_BINS_256 3
Tao Baod7db5942015-01-28 10:07:51 -0800102#define OMAP3ISP_HIST_MEM_SIZE_BINS(n) ((1 << ((n) + 5)) * 4 * 4)
Ben Cheng655a7c02013-10-16 16:09:24 -0700103#define OMAP3ISP_HIST_MEM_SIZE 1024
104#define OMAP3ISP_HIST_MIN_REGIONS 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700105#define OMAP3ISP_HIST_MAX_REGIONS 4
106#define OMAP3ISP_HIST_MAX_WB_GAIN 255
107#define OMAP3ISP_HIST_MIN_WB_GAIN 0
108#define OMAP3ISP_HIST_MAX_BIT_WIDTH 14
Ben Cheng655a7c02013-10-16 16:09:24 -0700109#define OMAP3ISP_HIST_MIN_BIT_WIDTH 8
110#define OMAP3ISP_HIST_MAX_WG 4
111#define OMAP3ISP_HIST_MAX_BUF_SIZE 4096
112#define OMAP3ISP_HIST_SOURCE_CCDC 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700113#define OMAP3ISP_HIST_SOURCE_MEM 1
114#define OMAP3ISP_HIST_CFA_BAYER 0
115#define OMAP3ISP_HIST_CFA_FOVEONX3 1
116struct omap3isp_hist_region {
Tao Baod7db5942015-01-28 10:07:51 -0800117 __u16 h_start;
118 __u16 h_end;
119 __u16 v_start;
120 __u16 v_end;
Ben Cheng655a7c02013-10-16 16:09:24 -0700121};
122struct omap3isp_hist_config {
Tao Baod7db5942015-01-28 10:07:51 -0800123 __u32 buf_size;
124 __u16 config_counter;
Tao Baod7db5942015-01-28 10:07:51 -0800125 __u8 num_acc_frames;
126 __u16 hist_bins;
127 __u8 cfa;
128 __u8 wg[OMAP3ISP_HIST_MAX_WG];
Tao Baod7db5942015-01-28 10:07:51 -0800129 __u8 num_regions;
130 struct omap3isp_hist_region region[OMAP3ISP_HIST_MAX_REGIONS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700131};
132#define OMAP3ISP_AF_NUM_COEF 11
Ben Cheng655a7c02013-10-16 16:09:24 -0700133enum omap3isp_h3a_af_fvmode {
Tao Baod7db5942015-01-28 10:07:51 -0800134 OMAP3ISP_AF_MODE_SUMMED = 0,
135 OMAP3ISP_AF_MODE_PEAK = 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700136};
Ben Cheng655a7c02013-10-16 16:09:24 -0700137enum omap3isp_h3a_af_rgbpos {
Tao Baod7db5942015-01-28 10:07:51 -0800138 OMAP3ISP_AF_GR_GB_BAYER = 0,
139 OMAP3ISP_AF_RG_GB_BAYER = 1,
140 OMAP3ISP_AF_GR_BG_BAYER = 2,
Tao Baod7db5942015-01-28 10:07:51 -0800141 OMAP3ISP_AF_RG_BG_BAYER = 3,
142 OMAP3ISP_AF_GG_RB_CUSTOM = 4,
143 OMAP3ISP_AF_RB_GG_CUSTOM = 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700144};
Ben Cheng655a7c02013-10-16 16:09:24 -0700145struct omap3isp_h3a_af_hmf {
Tao Baod7db5942015-01-28 10:07:51 -0800146 __u8 enable;
147 __u8 threshold;
Ben Cheng655a7c02013-10-16 16:09:24 -0700148};
Ben Cheng655a7c02013-10-16 16:09:24 -0700149struct omap3isp_h3a_af_iir {
Tao Baod7db5942015-01-28 10:07:51 -0800150 __u16 h_start;
151 __u16 coeff_set0[OMAP3ISP_AF_NUM_COEF];
152 __u16 coeff_set1[OMAP3ISP_AF_NUM_COEF];
Ben Cheng655a7c02013-10-16 16:09:24 -0700153};
154struct omap3isp_h3a_af_paxel {
Tao Baod7db5942015-01-28 10:07:51 -0800155 __u16 h_start;
156 __u16 v_start;
Tao Baod7db5942015-01-28 10:07:51 -0800157 __u8 width;
158 __u8 height;
159 __u8 h_cnt;
160 __u8 v_cnt;
Tao Baod7db5942015-01-28 10:07:51 -0800161 __u8 line_inc;
Ben Cheng655a7c02013-10-16 16:09:24 -0700162};
163struct omap3isp_h3a_af_config {
Tao Baod7db5942015-01-28 10:07:51 -0800164 __u32 buf_size;
Tao Baod7db5942015-01-28 10:07:51 -0800165 __u16 config_counter;
166 struct omap3isp_h3a_af_hmf hmf;
167 struct omap3isp_h3a_af_iir iir;
168 struct omap3isp_h3a_af_paxel paxel;
Tao Baod7db5942015-01-28 10:07:51 -0800169 enum omap3isp_h3a_af_rgbpos rgb_pos;
170 enum omap3isp_h3a_af_fvmode fvmode;
171 __u8 alaw_enable;
Ben Cheng655a7c02013-10-16 16:09:24 -0700172};
Ben Cheng655a7c02013-10-16 16:09:24 -0700173#define OMAP3ISP_CCDC_ALAW (1 << 0)
174#define OMAP3ISP_CCDC_LPF (1 << 1)
175#define OMAP3ISP_CCDC_BLCLAMP (1 << 2)
176#define OMAP3ISP_CCDC_BCOMP (1 << 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700177#define OMAP3ISP_CCDC_FPC (1 << 4)
178#define OMAP3ISP_CCDC_CULL (1 << 5)
179#define OMAP3ISP_CCDC_CONFIG_LSC (1 << 7)
180#define OMAP3ISP_CCDC_TBL_LSC (1 << 8)
Ben Cheng655a7c02013-10-16 16:09:24 -0700181#define OMAP3ISP_RGB_MAX 3
182enum omap3isp_alaw_ipwidth {
Tao Baod7db5942015-01-28 10:07:51 -0800183 OMAP3ISP_ALAW_BIT12_3 = 0x3,
184 OMAP3ISP_ALAW_BIT11_2 = 0x4,
Tao Baod7db5942015-01-28 10:07:51 -0800185 OMAP3ISP_ALAW_BIT10_1 = 0x5,
186 OMAP3ISP_ALAW_BIT9_0 = 0x6
Ben Cheng655a7c02013-10-16 16:09:24 -0700187};
188struct omap3isp_ccdc_lsc_config {
Tao Baod7db5942015-01-28 10:07:51 -0800189 __u16 offset;
190 __u8 gain_mode_n;
191 __u8 gain_mode_m;
192 __u8 gain_format;
Tao Baod7db5942015-01-28 10:07:51 -0800193 __u16 fmtsph;
194 __u16 fmtlnh;
195 __u16 fmtslv;
196 __u16 fmtlnv;
Tao Baod7db5942015-01-28 10:07:51 -0800197 __u8 initial_x;
198 __u8 initial_y;
199 __u32 size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700200};
Ben Cheng655a7c02013-10-16 16:09:24 -0700201struct omap3isp_ccdc_bclamp {
Tao Baod7db5942015-01-28 10:07:51 -0800202 __u8 obgain;
203 __u8 obstpixel;
204 __u8 oblines;
Tao Baod7db5942015-01-28 10:07:51 -0800205 __u8 oblen;
206 __u16 dcsubval;
Ben Cheng655a7c02013-10-16 16:09:24 -0700207};
208struct omap3isp_ccdc_fpc {
Tao Baod7db5942015-01-28 10:07:51 -0800209 __u16 fpnum;
210 __u32 fpcaddr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700211};
212struct omap3isp_ccdc_blcomp {
Tao Baod7db5942015-01-28 10:07:51 -0800213 __u8 b_mg;
214 __u8 gb_g;
215 __u8 gr_cy;
216 __u8 r_ye;
Ben Cheng655a7c02013-10-16 16:09:24 -0700217};
218struct omap3isp_ccdc_culling {
Tao Baod7db5942015-01-28 10:07:51 -0800219 __u8 v_pattern;
220 __u16 h_odd;
Tao Baod7db5942015-01-28 10:07:51 -0800221 __u16 h_even;
Ben Cheng655a7c02013-10-16 16:09:24 -0700222};
223struct omap3isp_ccdc_update_config {
Tao Baod7db5942015-01-28 10:07:51 -0800224 __u16 update;
Tao Baod7db5942015-01-28 10:07:51 -0800225 __u16 flag;
226 enum omap3isp_alaw_ipwidth alawip;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700227 struct omap3isp_ccdc_bclamp * bclamp;
228 struct omap3isp_ccdc_blcomp * blcomp;
229 struct omap3isp_ccdc_fpc * fpc;
230 struct omap3isp_ccdc_lsc_config * lsc_cfg;
231 struct omap3isp_ccdc_culling * cull;
232 __u8 * lsc;
Ben Cheng655a7c02013-10-16 16:09:24 -0700233};
234#define OMAP3ISP_PREV_LUMAENH (1 << 0)
235#define OMAP3ISP_PREV_INVALAW (1 << 1)
236#define OMAP3ISP_PREV_HRZ_MED (1 << 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700237#define OMAP3ISP_PREV_CFA (1 << 3)
238#define OMAP3ISP_PREV_CHROMA_SUPP (1 << 4)
239#define OMAP3ISP_PREV_WB (1 << 5)
240#define OMAP3ISP_PREV_BLKADJ (1 << 6)
Ben Cheng655a7c02013-10-16 16:09:24 -0700241#define OMAP3ISP_PREV_RGB2RGB (1 << 7)
242#define OMAP3ISP_PREV_COLOR_CONV (1 << 8)
243#define OMAP3ISP_PREV_YC_LIMIT (1 << 9)
244#define OMAP3ISP_PREV_DEFECT_COR (1 << 10)
Ben Cheng655a7c02013-10-16 16:09:24 -0700245#define OMAP3ISP_PREV_DRK_FRM_CAPTURE (1 << 12)
246#define OMAP3ISP_PREV_DRK_FRM_SUBTRACT (1 << 13)
247#define OMAP3ISP_PREV_LENS_SHADING (1 << 14)
248#define OMAP3ISP_PREV_NF (1 << 15)
Ben Cheng655a7c02013-10-16 16:09:24 -0700249#define OMAP3ISP_PREV_GAMMA (1 << 16)
250#define OMAP3ISP_PREV_NF_TBL_SIZE 64
251#define OMAP3ISP_PREV_CFA_TBL_SIZE 576
252#define OMAP3ISP_PREV_CFA_BLK_SIZE (OMAP3ISP_PREV_CFA_TBL_SIZE / 4)
Ben Cheng655a7c02013-10-16 16:09:24 -0700253#define OMAP3ISP_PREV_GAMMA_TBL_SIZE 1024
254#define OMAP3ISP_PREV_YENH_TBL_SIZE 128
255#define OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS 4
256struct omap3isp_prev_hmed {
Tao Baod7db5942015-01-28 10:07:51 -0800257 __u8 odddist;
258 __u8 evendist;
259 __u8 thres;
Ben Cheng655a7c02013-10-16 16:09:24 -0700260};
Ben Cheng655a7c02013-10-16 16:09:24 -0700261enum omap3isp_cfa_fmt {
Tao Baod7db5942015-01-28 10:07:51 -0800262 OMAP3ISP_CFAFMT_BAYER,
263 OMAP3ISP_CFAFMT_SONYVGA,
264 OMAP3ISP_CFAFMT_RGBFOVEON,
Tao Baod7db5942015-01-28 10:07:51 -0800265 OMAP3ISP_CFAFMT_DNSPL,
266 OMAP3ISP_CFAFMT_HONEYCOMB,
267 OMAP3ISP_CFAFMT_RRGGBBFOVEON
Ben Cheng655a7c02013-10-16 16:09:24 -0700268};
Ben Cheng655a7c02013-10-16 16:09:24 -0700269struct omap3isp_prev_cfa {
Tao Baod7db5942015-01-28 10:07:51 -0800270 enum omap3isp_cfa_fmt format;
271 __u8 gradthrs_vert;
272 __u8 gradthrs_horz;
Tao Baod7db5942015-01-28 10:07:51 -0800273 __u32 table[4][OMAP3ISP_PREV_CFA_BLK_SIZE];
Ben Cheng655a7c02013-10-16 16:09:24 -0700274};
275struct omap3isp_prev_csup {
Tao Baod7db5942015-01-28 10:07:51 -0800276 __u8 gain;
Tao Baod7db5942015-01-28 10:07:51 -0800277 __u8 thres;
278 __u8 hypf_en;
Ben Cheng655a7c02013-10-16 16:09:24 -0700279};
280struct omap3isp_prev_wbal {
Tao Baod7db5942015-01-28 10:07:51 -0800281 __u16 dgain;
282 __u8 coef3;
283 __u8 coef2;
284 __u8 coef1;
Tao Baod7db5942015-01-28 10:07:51 -0800285 __u8 coef0;
Ben Cheng655a7c02013-10-16 16:09:24 -0700286};
287struct omap3isp_prev_blkadj {
Tao Baod7db5942015-01-28 10:07:51 -0800288 __u8 red;
Tao Baod7db5942015-01-28 10:07:51 -0800289 __u8 green;
290 __u8 blue;
Ben Cheng655a7c02013-10-16 16:09:24 -0700291};
292struct omap3isp_prev_rgbtorgb {
Tao Baod7db5942015-01-28 10:07:51 -0800293 __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX];
294 __u16 offset[OMAP3ISP_RGB_MAX];
Ben Cheng655a7c02013-10-16 16:09:24 -0700295};
296struct omap3isp_prev_csc {
Tao Baod7db5942015-01-28 10:07:51 -0800297 __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX];
298 __s16 offset[OMAP3ISP_RGB_MAX];
Ben Cheng655a7c02013-10-16 16:09:24 -0700299};
300struct omap3isp_prev_yclimit {
Tao Baod7db5942015-01-28 10:07:51 -0800301 __u8 minC;
302 __u8 maxC;
303 __u8 minY;
304 __u8 maxY;
Ben Cheng655a7c02013-10-16 16:09:24 -0700305};
306struct omap3isp_prev_dcor {
Tao Baod7db5942015-01-28 10:07:51 -0800307 __u8 couplet_mode_en;
308 __u32 detect_correct[OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700309};
310struct omap3isp_prev_nf {
Tao Baod7db5942015-01-28 10:07:51 -0800311 __u8 spread;
312 __u32 table[OMAP3ISP_PREV_NF_TBL_SIZE];
Ben Cheng655a7c02013-10-16 16:09:24 -0700313};
314struct omap3isp_prev_gtables {
Tao Baod7db5942015-01-28 10:07:51 -0800315 __u32 red[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
316 __u32 green[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
Tao Baod7db5942015-01-28 10:07:51 -0800317 __u32 blue[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
Ben Cheng655a7c02013-10-16 16:09:24 -0700318};
319struct omap3isp_prev_luma {
Tao Baod7db5942015-01-28 10:07:51 -0800320 __u32 table[OMAP3ISP_PREV_YENH_TBL_SIZE];
Ben Cheng655a7c02013-10-16 16:09:24 -0700321};
322struct omap3isp_prev_update_config {
Tao Baod7db5942015-01-28 10:07:51 -0800323 __u32 update;
324 __u32 flag;
Tao Baod7db5942015-01-28 10:07:51 -0800325 __u32 shading_shift;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700326 struct omap3isp_prev_luma * luma;
327 struct omap3isp_prev_hmed * hmed;
328 struct omap3isp_prev_cfa * cfa;
329 struct omap3isp_prev_csup * csup;
330 struct omap3isp_prev_wbal * wbal;
331 struct omap3isp_prev_blkadj * blkadj;
332 struct omap3isp_prev_rgbtorgb * rgb2rgb;
333 struct omap3isp_prev_csc * csc;
334 struct omap3isp_prev_yclimit * yclimit;
335 struct omap3isp_prev_dcor * dcor;
336 struct omap3isp_prev_nf * nf;
337 struct omap3isp_prev_gtables * gamma;
Ben Cheng655a7c02013-10-16 16:09:24 -0700338};
339#endif