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gerrit.omnirom.org / android_bionic / 05d08e9716b5974d6ed08973f44930804890b902 / . / libc / kernel / uapi / sound / emu10k1.h
blob: b03fce6ad34ac022a9c37931f290234c3c50f9bc [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI__SOUND_EMU10K1_H
20#define _UAPI__SOUND_EMU10K1_H
21#include <linux/types.h>
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]22#include <sound/asound.h>
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]24#define EMU10K1_CARD_CREATIVE 0x00000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]25#define EMU10K1_CARD_EMUAPS 0x00000001
26#define EMU10K1_FX8010_PCM_COUNT 8
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]27#define __EMU10K1_DECLARE_BITMAP(name,bits) unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29#define iMAC0 0x00
30#define iMAC1 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]31#define iMAC2 0x02
32#define iMAC3 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34#define iMACINT0 0x04
35#define iMACINT1 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]36#define iACC3 0x06
37#define iMACMV 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39#define iANDXOR 0x08
40#define iTSTNEG 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]41#define iLIMITGE 0x0a
42#define iLIMITLT 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]44#define iLOG 0x0c
45#define iEXP 0x0d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]46#define iINTERP 0x0e
47#define iSKIP 0x0f
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49#define FXBUS(x) (0x00 + (x))
50#define EXTIN(x) (0x10 + (x))
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]51#define EXTOUT(x) (0x20 + (x))
52#define FXBUS2(x) (0x30 + (x))
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]54#define C_00000000 0x40
55#define C_00000001 0x41
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]56#define C_00000002 0x42
57#define C_00000003 0x43
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]59#define C_00000004 0x44
60#define C_00000008 0x45
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]61#define C_00000010 0x46
62#define C_00000020 0x47
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64#define C_00000100 0x48
65#define C_00010000 0x49
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]66#define C_00080000 0x4a
67#define C_10000000 0x4b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69#define C_20000000 0x4c
70#define C_40000000 0x4d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]71#define C_80000000 0x4e
72#define C_7fffffff 0x4f
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74#define C_ffffffff 0x50
75#define C_fffffffe 0x51
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]76#define C_c0000000 0x52
77#define C_4f1bbcdc 0x53
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]79#define C_5a7ef9db 0x54
80#define C_00100000 0x55
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]81#define GPR_ACCU 0x56
82#define GPR_COND 0x57
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84#define GPR_NOISE0 0x58
85#define GPR_NOISE1 0x59
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]86#define GPR_IRQ 0x5a
87#define GPR_DBAC 0x5b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89#define GPR(x) (FXGPREGBASE + (x))
90#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]91#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x))
92#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x))
95#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]96#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x))
97#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x))
100#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x))
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]101#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x))
102#define A_FXBUS(x) (0x00 + (x))
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]104#define A_EXTIN(x) (0x40 + (x))
105#define A_P16VIN(x) (0x50 + (x))
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]106#define A_EXTOUT(x) (0x60 + (x))
107#define A_FXBUS2(x) (0x80 + (x))
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109#define A_EMU32OUTH(x) (0xa0 + (x))
110#define A_EMU32OUTL(x) (0xb0 + (x))
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]111#define A3_EMU32IN(x) (0x160 + (x))
112#define A3_EMU32OUT(x) (0x1E0 + (x))
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]114#define A_GPR(x) (A_FXGPREGBASE + (x))
115#define CC_REG_NORMALIZED C_00000001
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]116#define CC_REG_BORROW C_00000002
117#define CC_REG_MINUS C_00000004
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119#define CC_REG_ZERO C_00000008
120#define CC_REG_SATURATE C_00000010
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]121#define CC_REG_NONZERO C_00000100
122#define FXBUS_PCM_LEFT 0x00
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124#define FXBUS_PCM_RIGHT 0x01
125#define FXBUS_PCM_LEFT_REAR 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]126#define FXBUS_PCM_RIGHT_REAR 0x03
127#define FXBUS_MIDI_LEFT 0x04
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129#define FXBUS_MIDI_RIGHT 0x05
130#define FXBUS_PCM_CENTER 0x06
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]131#define FXBUS_PCM_LFE 0x07
132#define FXBUS_PCM_LEFT_FRONT 0x08
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134#define FXBUS_PCM_RIGHT_FRONT 0x09
135#define FXBUS_MIDI_REVERB 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]136#define FXBUS_MIDI_CHORUS 0x0d
137#define FXBUS_PCM_LEFT_SIDE 0x0e
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139#define FXBUS_PCM_RIGHT_SIDE 0x0f
140#define FXBUS_PT_LEFT 0x14
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]141#define FXBUS_PT_RIGHT 0x15
142#define EXTIN_AC97_L 0x00
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144#define EXTIN_AC97_R 0x01
145#define EXTIN_SPDIF_CD_L 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]146#define EXTIN_SPDIF_CD_R 0x03
147#define EXTIN_ZOOM_L 0x04
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149#define EXTIN_ZOOM_R 0x05
150#define EXTIN_TOSLINK_L 0x06
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]151#define EXTIN_TOSLINK_R 0x07
152#define EXTIN_LINE1_L 0x08
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154#define EXTIN_LINE1_R 0x09
155#define EXTIN_COAX_SPDIF_L 0x0a
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]156#define EXTIN_COAX_SPDIF_R 0x0b
157#define EXTIN_LINE2_L 0x0c
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]159#define EXTIN_LINE2_R 0x0d
160#define EXTOUT_AC97_L 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]161#define EXTOUT_AC97_R 0x01
162#define EXTOUT_TOSLINK_L 0x02
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]164#define EXTOUT_TOSLINK_R 0x03
165#define EXTOUT_AC97_CENTER 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]166#define EXTOUT_AC97_LFE 0x05
167#define EXTOUT_HEADPHONE_L 0x06
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]169#define EXTOUT_HEADPHONE_R 0x07
170#define EXTOUT_REAR_L 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]171#define EXTOUT_REAR_R 0x09
172#define EXTOUT_ADC_CAP_L 0x0a
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174#define EXTOUT_ADC_CAP_R 0x0b
175#define EXTOUT_MIC_CAP 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]176#define EXTOUT_AC97_REAR_L 0x0d
177#define EXTOUT_AC97_REAR_R 0x0e
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179#define EXTOUT_ACENTER 0x11
180#define EXTOUT_ALFE 0x12
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]181#define A_EXTIN_AC97_L 0x00
182#define A_EXTIN_AC97_R 0x01
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define A_EXTIN_SPDIF_CD_L 0x02
185#define A_EXTIN_SPDIF_CD_R 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]186#define A_EXTIN_OPT_SPDIF_L 0x04
187#define A_EXTIN_OPT_SPDIF_R 0x05
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189#define A_EXTIN_LINE2_L 0x08
190#define A_EXTIN_LINE2_R 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]191#define A_EXTIN_ADC_L 0x0a
192#define A_EXTIN_ADC_R 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194#define A_EXTIN_AUX2_L 0x0c
195#define A_EXTIN_AUX2_R 0x0d
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]196#define A_EXTOUT_FRONT_L 0x00
197#define A_EXTOUT_FRONT_R 0x01
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]199#define A_EXTOUT_CENTER 0x02
200#define A_EXTOUT_LFE 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]201#define A_EXTOUT_HEADPHONE_L 0x04
202#define A_EXTOUT_HEADPHONE_R 0x05
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]204#define A_EXTOUT_REAR_L 0x06
205#define A_EXTOUT_REAR_R 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]206#define A_EXTOUT_AFRONT_L 0x08
207#define A_EXTOUT_AFRONT_R 0x09
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]209#define A_EXTOUT_ACENTER 0x0a
210#define A_EXTOUT_ALFE 0x0b
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]211#define A_EXTOUT_ASIDE_L 0x0c
212#define A_EXTOUT_ASIDE_R 0x0d
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214#define A_EXTOUT_AREAR_L 0x0e
215#define A_EXTOUT_AREAR_R 0x0f
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]216#define A_EXTOUT_AC97_L 0x10
217#define A_EXTOUT_AC97_R 0x11
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define A_EXTOUT_ADC_CAP_L 0x16
220#define A_EXTOUT_ADC_CAP_R 0x17
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]221#define A_EXTOUT_MIC_CAP 0x18
222#define A_C_00000000 0xc0
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224#define A_C_00000001 0xc1
225#define A_C_00000002 0xc2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]226#define A_C_00000003 0xc3
227#define A_C_00000004 0xc4
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]229#define A_C_00000008 0xc5
230#define A_C_00000010 0xc6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]231#define A_C_00000020 0xc7
232#define A_C_00000100 0xc8
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]234#define A_C_00010000 0xc9
235#define A_C_00000800 0xca
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]236#define A_C_10000000 0xcb
237#define A_C_20000000 0xcc
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]239#define A_C_40000000 0xcd
240#define A_C_80000000 0xce
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]241#define A_C_7fffffff 0xcf
242#define A_C_ffffffff 0xd0
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]244#define A_C_fffffffe 0xd1
245#define A_C_c0000000 0xd2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]246#define A_C_4f1bbcdc 0xd3
247#define A_C_5a7ef9db 0xd4
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]249#define A_C_00100000 0xd5
250#define A_GPR_ACCU 0xd6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]251#define A_GPR_COND 0xd7
252#define A_GPR_NOISE0 0xd8
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]254#define A_GPR_NOISE1 0xd9
255#define A_GPR_IRQ 0xda
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]256#define A_GPR_DBAC 0xdb
257#define A_GPR_DBACE 0xde
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]259#define EMU10K1_DBG_ZC 0x80000000
260#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]261#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000
262#define EMU10K1_DBG_SINGLE_STEP 0x00008000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]264#define EMU10K1_DBG_STEP 0x00004000
265#define EMU10K1_DBG_CONDITION_CODE 0x00003e00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]266#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff
267#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]269#define TANKMEMADDRREG_CLEAR 0x00800000
270#define TANKMEMADDRREG_ALIGN 0x00400000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]271#define TANKMEMADDRREG_WRITE 0x00200000
272#define TANKMEMADDRREG_READ 0x00100000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]274struct snd_emu10k1_fx8010_info {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]275 unsigned int internal_tram_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]276 unsigned int external_tram_size;
277 char fxbus_names[16][32];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]279 char extin_names[16][32];
280 char extout_names[32][32];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]281 unsigned int gpr_controls;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]282};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]284#define EMU10K1_GPR_TRANSLATION_NONE 0
285#define EMU10K1_GPR_TRANSLATION_TABLE100 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]286#define EMU10K1_GPR_TRANSLATION_BASS 2
287#define EMU10K1_GPR_TRANSLATION_TREBLE 3
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]289#define EMU10K1_GPR_TRANSLATION_ONOFF 4
290struct snd_emu10k1_fx8010_control_gpr {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]291 struct snd_ctl_elem_id id;
292 unsigned int vcount;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]294 unsigned int count;
295 unsigned short gpr[32];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]296 unsigned int value[32];
297 unsigned int min;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]299 unsigned int max;
300 unsigned int translation;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]301 const unsigned int * tlv;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]302};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]304struct snd_emu10k1_fx8010_control_old_gpr {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]305 struct snd_ctl_elem_id id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]306 unsigned int vcount;
307 unsigned int count;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]309 unsigned short gpr[32];
310 unsigned int value[32];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]311 unsigned int min;
312 unsigned int max;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]314 unsigned int translation;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]315};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]316struct snd_emu10k1_fx8010_code {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]317 char name[128];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]319 __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200);
320 __u32 __user * gpr_map;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]321 unsigned int gpr_add_control_count;
322 struct snd_emu10k1_fx8010_control_gpr __user * gpr_add_controls;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]324 unsigned int gpr_del_control_count;
325 struct snd_ctl_elem_id __user * gpr_del_controls;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]326 unsigned int gpr_list_control_count;
327 unsigned int gpr_list_control_total;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]329 struct snd_emu10k1_fx8010_control_gpr __user * gpr_list_controls;
330 __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100);
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]331 __u32 __user * tram_data_map;
332 __u32 __user * tram_addr_map;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]334 __EMU10K1_DECLARE_BITMAP(code_valid, 1024);
335 __u32 __user * code;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]336};
337struct snd_emu10k1_fx8010_tram {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]339 unsigned int address;
340 unsigned int size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]341 unsigned int * samples;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]342};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]344struct snd_emu10k1_fx8010_pcm_rec {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]345 unsigned int substream;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]346 unsigned int res1;
347 unsigned int channels;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]349 unsigned int tram_start;
350 unsigned int buffer_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]351 unsigned short gpr_size;
352 unsigned short gpr_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]354 unsigned short gpr_count;
355 unsigned short gpr_tmpcount;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]356 unsigned short gpr_trigger;
357 unsigned short gpr_running;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]359 unsigned char pad;
360 unsigned char etram[32];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]361 unsigned int res2;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]362};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]364#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]365#define SNDRV_EMU10K1_IOCTL_INFO _IOR('H', 0x10, struct snd_emu10k1_fx8010_info)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]366#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW('H', 0x11, struct snd_emu10k1_fx8010_code)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]367#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]369#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW('H', 0x20, int)
370#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW('H', 0x21, struct snd_emu10k1_fx8010_tram)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]371#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]372#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]374#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]375#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR('H', 0x40, int)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]376#define SNDRV_EMU10K1_IOCTL_STOP _IO('H', 0x80)
377#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO('H', 0x81)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]379#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO('H', 0x82)
380#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW('H', 0x83, int)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]381#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR('H', 0x84, int)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]382typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]384typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
385typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]386typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
387typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]389#endif