Revert "Add MIPS64r6 support for libpixelflinger"
This reverts commit ab5265ebe65eac3b9555eaa3f425cf8e2759d3b3.
This broke the mips64 build (which, stupidly, I hadn't tested):
system/core/libpixelflinger/codeflinger/MIPS64Assembler.h:24:35: fatal error: tinyutils/KeyedVector.h: No such file or directory
#include "tinyutils/KeyedVector.h"
Change-Id: I4fa1c04e196592fd1ef893a83c75261a55d32290
diff --git a/libpixelflinger/codeflinger/GGLAssembler.cpp b/libpixelflinger/codeflinger/GGLAssembler.cpp
index 346779f..325caba 100644
--- a/libpixelflinger/codeflinger/GGLAssembler.cpp
+++ b/libpixelflinger/codeflinger/GGLAssembler.cpp
@@ -893,8 +893,7 @@
return;
}
- if ((getCodegenArch() == CODEGEN_ARCH_MIPS) ||
- (getCodegenArch() == CODEGEN_ARCH_MIPS64)) {
+ if (getCodegenArch() == CODEGEN_ARCH_MIPS) {
// MIPS can do 16-bit imm in 1 instr, 32-bit in 3 instr
// the below ' while (mask)' code is buggy on mips
// since mips returns true on isValidImmediate()
@@ -1058,8 +1057,7 @@
RegisterAllocator::RegisterFile::RegisterFile(int codegen_arch)
: mRegs(0), mTouched(0), mStatus(0), mArch(codegen_arch), mRegisterOffset(0)
{
- if ((mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS) ||
- (mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS64)) {
+ if (mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS) {
mRegisterOffset = 2; // ARM has regs 0..15, MIPS offset to 2..17
}
reserve(ARMAssemblerInterface::SP);
@@ -1069,8 +1067,7 @@
RegisterAllocator::RegisterFile::RegisterFile(const RegisterFile& rhs, int codegen_arch)
: mRegs(rhs.mRegs), mTouched(rhs.mTouched), mArch(codegen_arch), mRegisterOffset(0)
{
- if ((mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS) ||
- (mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS64)) {
+ if (mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS) {
mRegisterOffset = 2; // ARM has regs 0..15, MIPS offset to 2..17
}
}