commit 414df3e583c21023a22a11b64e703cd4ab38b29a
author Yabin Cui <yabinc@google.com> Wed Mar 14 18:16:22 2018 -0700
committer Christopher Ferris <cferris@google.com> Mon Mar 19 11:11:19 2018 -0700
tree d5b85e94fd4df26e08236d430b73c5a0fd06eb02
parent 8dca85f0c81e18e73aad914c0c22c111ecfd32bc

Always set the sp reg to the cfa for DWARF.

There are a few places where it is assumed that this register is
set to the cfa value when interpreting DWARF information.

Add a testcase for unwinding art_quick_osr_stub on ARM.

Bug: 73954823

Test: Ran libunwindstack/libbacktrace unit tests.
Test: Random debuggerd -b of process on a hikey.
Test: Ran the 137 art test on host.
Change-Id: Ida6ccdc38c3cfeea6b57fe861a0cc127b150b790
(cherry picked from commit 11e96fe48a74e6ab97d4de899684d3a61a9d1129)

libunwindstack/tests/DwarfOpTest.cpp

diff --git a/libunwindstack/tests/DwarfOpTest.cpp b/libunwindstack/tests/DwarfOpTest.cpp
index 6e15227..d424d5f 100644
--- a/libunwindstack/tests/DwarfOpTest.cpp
+++ b/libunwindstack/tests/DwarfOpTest.cpp
@@ -1468,7 +1468,7 @@
   }
   this->op_memory_.SetMemory(0, opcode_buffer);
 
-  RegsImplFake<TypeParam> regs(32, 10);
+  RegsImplFake<TypeParam> regs(32);
   for (size_t i = 0; i < 32; i++) {
     regs[i] = i + 10;
   }
@@ -1499,7 +1499,7 @@
   };
   this->op_memory_.SetMemory(0, opcode_buffer);
 
-  RegsImplFake<TypeParam> regs(16, 10);
+  RegsImplFake<TypeParam> regs(16);
   for (size_t i = 0; i < 16; i++) {
     regs[i] = i + 10;
   }
@@ -1526,7 +1526,7 @@
                                         0x92, 0x80, 0x15, 0x80, 0x02};
   this->op_memory_.SetMemory(0, opcode_buffer);
 
-  RegsImplFake<TypeParam> regs(10, 10);
+  RegsImplFake<TypeParam> regs(10);
   regs[5] = 0x45;
   regs[6] = 0x190;
   RegsInfo<TypeParam> regs_info(&regs);