commit 3f4d036cb6d9484c1b98a1bd4476756f3ed6fa3c
author haocheng.zy@linux.alibaba.com <zhy811223@gmail.com> Sat Sep 10 11:38:19 2022 +0800
committer Elliott Hughes <enh@google.com> Sat Oct 29 14:57:23 2022 +0000
tree a209ea2c1590675e00a7f5e6c98c6a4cfc10507a
parent c8c24a7255f6b20cb57337cef27652518bebd64e

Add riscv support for heap_addr_in_register

Change-Id: I42a93a96c8c9c7a32d32674535ff466380e3c2fa
Signed-off-by: haocheng.zy <haocheng.zy@linux.alibaba.com>

debuggerd/debuggerd_test.cpp

diff --git a/debuggerd/debuggerd_test.cpp b/debuggerd/debuggerd_test.cpp
index c08721b..9c1b136 100644
--- a/debuggerd/debuggerd_test.cpp
+++ b/debuggerd/debuggerd_test.cpp
@@ -445,6 +445,8 @@
   ASSERT_MATCH(result, "memory near x0 \\(\\[anon:");
 #elif defined(__arm__)
   ASSERT_MATCH(result, "memory near r0 \\(\\[anon:");
+#elif defined(__riscv)
+  ASSERT_MATCH(result, "memory near a0 \\(\\[anon:");
 #elif defined(__x86_64__)
   ASSERT_MATCH(result, "memory near rdi \\(\\[anon:");
 #else