Merge "riscv64: fix debuggerd_test build."
diff --git a/debuggerd/Android.bp b/debuggerd/Android.bp
index dc31cb2..d20de6b 100644
--- a/debuggerd/Android.bp
+++ b/debuggerd/Android.bp
@@ -510,6 +510,9 @@
arm64: {
src: "seccomp_policy/crash_dump.arm.policy",
},
+ riscv64: {
+ enabled: false,
+ },
x86: {
src: "seccomp_policy/crash_dump.x86_64.policy",
},
diff --git a/debuggerd/debuggerd_test.cpp b/debuggerd/debuggerd_test.cpp
index 517f2df..a00a202 100644
--- a/debuggerd/debuggerd_test.cpp
+++ b/debuggerd/debuggerd_test.cpp
@@ -2437,35 +2437,42 @@
#if defined(__arm__)
asm volatile(
"mov r1, %[base]\n"
- "mov r2, 0\n"
- "str r3, [r2]\n"
+ "mov r2, #0\n"
+ "str r2, [r2]\n"
: [base] "+r"(ptr)
:
- : "r1", "r2", "r3", "memory");
+ : "r1", "r2", "memory");
#elif defined(__aarch64__)
asm volatile(
"mov x1, %[base]\n"
- "mov x2, 0\n"
- "str x3, [x2]\n"
+ "mov x2, #0\n"
+ "str xzr, [x2]\n"
: [base] "+r"(ptr)
:
- : "x1", "x2", "x3", "memory");
+ : "x1", "x2", "memory");
+#elif defined(__riscv)
+ // TODO: x1 is ra (the link register) on riscv64, so this might have
+ // unintended consequences, but we'll need to change the .cfi_escape if so.
+ asm volatile(
+ "mv x1, %[base]\n"
+ "sw zero, 0(zero)\n"
+ : [base] "+r"(ptr)
+ :
+ : "x1", "memory");
#elif defined(__i386__)
asm volatile(
"mov %[base], %%ecx\n"
- "movl $0, %%edi\n"
- "movl 0(%%edi), %%edx\n"
+ "movl $0, 0\n"
: [base] "+r"(ptr)
:
- : "edi", "ecx", "edx", "memory");
+ : "ecx", "memory");
#elif defined(__x86_64__)
asm volatile(
"mov %[base], %%rdx\n"
- "movq 0, %%rdi\n"
- "movq 0(%%rdi), %%rcx\n"
+ "movq $0, 0\n"
: [base] "+r"(ptr)
:
- : "rcx", "rdx", "rdi", "memory");
+ : "rdx", "memory");
#else
#error "Unsupported architecture"
#endif