Merge changes from topic "uevent"
* changes:
libcutils: Work around the lack of __mulodi4
libcutils: Make uevent_kernel_* namespace-aware
diff --git a/adb/daemon/main.cpp b/adb/daemon/main.cpp
index 1c94298..3c27582 100644
--- a/adb/daemon/main.cpp
+++ b/adb/daemon/main.cpp
@@ -233,8 +233,8 @@
adb_device_banner = optarg;
break;
case 'v':
- printf("Android Debug Bridge Daemon version %d.%d.%d (%s)\n", ADB_VERSION_MAJOR,
- ADB_VERSION_MINOR, ADB_SERVER_VERSION, ADB_VERSION);
+ printf("Android Debug Bridge Daemon version %d.%d.%d\n", ADB_VERSION_MAJOR,
+ ADB_VERSION_MINOR, ADB_SERVER_VERSION);
return 0;
default:
// getopt already prints "adbd: invalid option -- %c" for us.
diff --git a/debuggerd/debuggerd_test.cpp b/debuggerd/debuggerd_test.cpp
index 45e768d..8d0c98b 100644
--- a/debuggerd/debuggerd_test.cpp
+++ b/debuggerd/debuggerd_test.cpp
@@ -16,6 +16,7 @@
#include <err.h>
#include <fcntl.h>
+#include <stdlib.h>
#include <sys/capability.h>
#include <sys/prctl.h>
#include <sys/ptrace.h>
@@ -298,6 +299,26 @@
ASSERT_MATCH(result, R"(signal 11 \(SIGSEGV\), code 1 \(SEGV_MAPERR\), fault addr 0xdead)");
}
+TEST_F(CrasherTest, LD_PRELOAD) {
+ int intercept_result;
+ unique_fd output_fd;
+ StartProcess([]() {
+ setenv("LD_PRELOAD", "nonexistent.so", 1);
+ *reinterpret_cast<volatile char*>(0xdead) = '1';
+ });
+
+ StartIntercept(&output_fd);
+ FinishCrasher();
+ AssertDeath(SIGSEGV);
+ FinishIntercept(&intercept_result);
+
+ ASSERT_EQ(1, intercept_result) << "tombstoned reported failure";
+
+ std::string result;
+ ConsumeFd(std::move(output_fd), &result);
+ ASSERT_MATCH(result, R"(signal 11 \(SIGSEGV\), code 1 \(SEGV_MAPERR\), fault addr 0xdead)");
+}
+
TEST_F(CrasherTest, abort) {
int intercept_result;
unique_fd output_fd;
diff --git a/debuggerd/handler/debuggerd_handler.cpp b/debuggerd/handler/debuggerd_handler.cpp
index d41dc67..d6b6d58 100644
--- a/debuggerd/handler/debuggerd_handler.cpp
+++ b/debuggerd/handler/debuggerd_handler.cpp
@@ -330,8 +330,8 @@
async_safe_format_buffer(debuggerd_dump_type, sizeof(debuggerd_dump_type), "%d",
get_dump_type(thread_info));
- execl(CRASH_DUMP_PATH, CRASH_DUMP_NAME, main_tid, pseudothread_tid, debuggerd_dump_type,
- nullptr);
+ execle(CRASH_DUMP_PATH, CRASH_DUMP_NAME, main_tid, pseudothread_tid, debuggerd_dump_type,
+ nullptr, nullptr);
fatal_errno("exec failed");
} else {
diff --git a/fastboot/Android.mk b/fastboot/Android.mk
index dd8bad9..bc88002 100644
--- a/fastboot/Android.mk
+++ b/fastboot/Android.mk
@@ -58,7 +58,6 @@
LOCAL_STATIC_LIBRARIES := \
libziparchive \
- libext4_utils \
libsparse \
libutils \
liblog \
diff --git a/fastboot/fastboot.cpp b/fastboot/fastboot.cpp
index c3b1bfb..40c18e0 100644
--- a/fastboot/fastboot.cpp
+++ b/fastboot/fastboot.cpp
@@ -1354,7 +1354,7 @@
static unsigned fb_get_flash_block_size(Transport* transport, std::string name) {
std::string sizeString;
- if (!fb_getvar(transport, name.c_str(), &sizeString)) {
+ if (!fb_getvar(transport, name.c_str(), &sizeString) || sizeString.empty()) {
/* This device does not report flash block sizes, so return 0 */
return 0;
}
@@ -1365,9 +1365,8 @@
fprintf(stderr, "Couldn't parse %s '%s'.\n", name.c_str(), sizeString.c_str());
return 0;
}
- if (size < 4096 || (size & (size - 1)) != 0) {
- fprintf(stderr, "Invalid %s %u: must be a power of 2 and at least 4096.\n",
- name.c_str(), size);
+ if ((size & (size - 1)) != 0) {
+ fprintf(stderr, "Invalid %s %u: must be a power of 2.\n", name.c_str(), size);
return 0;
}
return size;
diff --git a/fastboot/fs.cpp b/fastboot/fs.cpp
index 709f061..2d77dd6 100644
--- a/fastboot/fs.cpp
+++ b/fastboot/fs.cpp
@@ -23,7 +23,6 @@
#include <android-base/file.h>
#include <android-base/stringprintf.h>
#include <android-base/unique_fd.h>
-#include <ext4_utils/make_ext4fs.h>
#include <sparse/sparse.h>
using android::base::StringPrintf;
@@ -120,6 +119,8 @@
int raid_stripe_width = eraseBlkSize / block_size;
// stride should be the max of 8kb and logical block size
if (logicalBlkSize != 0 && logicalBlkSize < 8192) raid_stride = 8192 / block_size;
+ // stripe width should be >= stride
+ if (raid_stripe_width < raid_stride) raid_stripe_width = raid_stride;
ext_attr += StringPrintf(",stride=%d,stripe-width=%d", raid_stride, raid_stripe_width);
}
mke2fs_args.push_back("-E");
diff --git a/libbacktrace/UnwindStack.cpp b/libbacktrace/UnwindStack.cpp
index d17c211..3a38839 100644
--- a/libbacktrace/UnwindStack.cpp
+++ b/libbacktrace/UnwindStack.cpp
@@ -44,13 +44,13 @@
#include "UnwindStackMap.h"
bool Backtrace::Unwind(unwindstack::Regs* regs, BacktraceMap* back_map,
- std::vector<backtrace_frame_data_t>* frames, size_t num_ignore_frames) {
- std::vector<std::string> skip_names{"libunwindstack.so", "libbacktrace.so"};
+ std::vector<backtrace_frame_data_t>* frames, size_t num_ignore_frames,
+ std::vector<std::string>* skip_names) {
UnwindStackMap* stack_map = reinterpret_cast<UnwindStackMap*>(back_map);
auto process_memory = stack_map->process_memory();
unwindstack::Unwinder unwinder(MAX_BACKTRACE_FRAMES + num_ignore_frames, stack_map->stack_maps(),
regs, stack_map->process_memory());
- unwinder.Unwind(&skip_names, &stack_map->GetSuffixesToIgnore());
+ unwinder.Unwind(skip_names, &stack_map->GetSuffixesToIgnore());
if (num_ignore_frames >= unwinder.NumFrames()) {
frames->resize(0);
@@ -104,7 +104,8 @@
}
error_ = BACKTRACE_UNWIND_NO_ERROR;
- return Backtrace::Unwind(regs.get(), GetMap(), &frames_, num_ignore_frames);
+ std::vector<std::string> skip_names{"libunwindstack.so", "libbacktrace.so"};
+ return Backtrace::Unwind(regs.get(), GetMap(), &frames_, num_ignore_frames, &skip_names);
}
UnwindStackPtrace::UnwindStackPtrace(pid_t pid, pid_t tid, BacktraceMap* map)
@@ -124,5 +125,5 @@
}
error_ = BACKTRACE_UNWIND_NO_ERROR;
- return Backtrace::Unwind(regs.get(), GetMap(), &frames_, num_ignore_frames);
+ return Backtrace::Unwind(regs.get(), GetMap(), &frames_, num_ignore_frames, nullptr);
}
diff --git a/libbacktrace/include/backtrace/Backtrace.h b/libbacktrace/include/backtrace/Backtrace.h
index 73a58b5..e073533 100644
--- a/libbacktrace/include/backtrace/Backtrace.h
+++ b/libbacktrace/include/backtrace/Backtrace.h
@@ -109,7 +109,8 @@
virtual bool Unwind(size_t num_ignore_frames, ucontext_t* context = NULL) = 0;
static bool Unwind(unwindstack::Regs* regs, BacktraceMap* back_map,
- std::vector<backtrace_frame_data_t>* frames, size_t num_ignore_frames);
+ std::vector<backtrace_frame_data_t>* frames, size_t num_ignore_frames,
+ std::vector<std::string>* skip_names);
// Get the function name and offset into the function given the pc.
// If the string is empty, then no valid function name was found,
diff --git a/libpixelflinger/Android.mk b/libpixelflinger/Android.mk
index 55891db..c7306cd 100644
--- a/libpixelflinger/Android.mk
+++ b/libpixelflinger/Android.mk
@@ -25,6 +25,8 @@
buffer.cpp
PIXELFLINGER_CFLAGS := -fstrict-aliasing -fomit-frame-pointer
+PIXELFLINGER_CFLAGS += -Wall -Werror
+PIXELFLINGER_CFLAGS += -Wno-unused-function
PIXELFLINGER_SRC_FILES_arm := \
codeflinger/ARMAssembler.cpp \
diff --git a/libpixelflinger/codeflinger/Arm64Assembler.cpp b/libpixelflinger/codeflinger/Arm64Assembler.cpp
index bff87bb..aebc129 100644
--- a/libpixelflinger/codeflinger/Arm64Assembler.cpp
+++ b/libpixelflinger/codeflinger/Arm64Assembler.cpp
@@ -151,11 +151,11 @@
namespace android {
-static const char* shift_codes[] =
+static __unused const char* shift_codes[] =
{
"LSL", "LSR", "ASR", "ROR"
};
-static const char *cc_codes[] =
+static __unused const char *cc_codes[] =
{
"EQ", "NE", "CS", "CC", "MI",
"PL", "VS", "VC", "HI", "LS",
@@ -984,7 +984,7 @@
// A64 instructions
// ----------------------------------------------------------------------------
-static const char * dataTransferOpName[] =
+static __unused const char * dataTransferOpName[] =
{
"LDR","LDRB","LDRH","STR","STRB","STRH"
};
diff --git a/libpixelflinger/codeflinger/GGLAssembler.cpp b/libpixelflinger/codeflinger/GGLAssembler.cpp
index 91fbd53..04e285d 100644
--- a/libpixelflinger/codeflinger/GGLAssembler.cpp
+++ b/libpixelflinger/codeflinger/GGLAssembler.cpp
@@ -94,8 +94,6 @@
int GGLAssembler::scanline_core(const needs_t& needs, context_t const* c)
{
- int64_t duration = ggl_system_time();
-
mBlendFactorCached = 0;
mBlending = 0;
mMasking = 0;
@@ -353,7 +351,6 @@
fragment_parts_t& parts, const needs_t& needs)
{
Scratch scratches(registerFile());
- int Rctx = mBuilderContext.Rctx;
// compute count
comment("compute ct (# of pixels to process)");
diff --git a/libpixelflinger/codeflinger/MIPS64Assembler.cpp b/libpixelflinger/codeflinger/MIPS64Assembler.cpp
index d5e4cea..d6d2156 100644
--- a/libpixelflinger/codeflinger/MIPS64Assembler.cpp
+++ b/libpixelflinger/codeflinger/MIPS64Assembler.cpp
@@ -39,6 +39,7 @@
#include "mips64_disassem.h"
#define NOT_IMPLEMENTED() LOG_ALWAYS_FATAL("Arm instruction %s not yet implemented\n", __func__)
+#define __unused __attribute__((__unused__))
// ----------------------------------------------------------------------------
@@ -146,7 +147,7 @@
mMips->MOVE(R_v0, R_a0); // move context * passed in a0 to v0 (arm r0)
}
-void ArmToMips64Assembler::epilog(uint32_t touched)
+void ArmToMips64Assembler::epilog(uint32_t touched __unused)
{
mArmPC[mInum++] = pc(); // save starting PC for this instr
@@ -205,7 +206,7 @@
// shifters...
-bool ArmToMips64Assembler::isValidImmediate(uint32_t immediate)
+bool ArmToMips64Assembler::isValidImmediate(uint32_t immediate __unused)
{
// for MIPS, any 32-bit immediate is OK
return true;
@@ -225,13 +226,14 @@
return AMODE_REG_IMM;
}
-uint32_t ArmToMips64Assembler::reg_rrx(int Rm)
+uint32_t ArmToMips64Assembler::reg_rrx(int Rm __unused)
{
// reg_rrx mode is not used in the GLLAssember code at this time
return AMODE_UNSUPPORTED;
}
-uint32_t ArmToMips64Assembler::reg_reg(int Rm, int type, int Rs)
+uint32_t ArmToMips64Assembler::reg_reg(int Rm __unused, int type __unused,
+ int Rs __unused)
{
// reg_reg mode is not used in the GLLAssember code at this time
return AMODE_UNSUPPORTED;
@@ -272,14 +274,15 @@
return AMODE_REG_SCALE_PRE;
}
-uint32_t ArmToMips64Assembler::reg_scale_post(int Rm, int type, uint32_t shift)
+uint32_t ArmToMips64Assembler::reg_scale_post(int Rm __unused, int type __unused,
+ uint32_t shift __unused)
{
LOG_ALWAYS_FATAL("adr mode reg_scale_post not yet implemented\n");
return AMODE_UNSUPPORTED;
}
// LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
-uint32_t ArmToMips64Assembler::immed8_pre(int32_t immed8, int W)
+uint32_t ArmToMips64Assembler::immed8_pre(int32_t immed8, int W __unused)
{
LOG_ALWAYS_FATAL("adr mode immed8_pre not yet implemented\n");
@@ -305,7 +308,7 @@
return AMODE_REG_PRE;
}
-uint32_t ArmToMips64Assembler::reg_post(int Rm)
+uint32_t ArmToMips64Assembler::reg_post(int Rm __unused)
{
LOG_ALWAYS_FATAL("adr mode reg_post not yet implemented\n");
return AMODE_UNSUPPORTED;
@@ -320,12 +323,6 @@
#pragma mark Data Processing...
#endif
-
-static const char * const dpOpNames[] = {
- "AND", "EOR", "SUB", "RSB", "ADD", "ADC", "SBC", "RSC",
- "TST", "TEQ", "CMP", "CMN", "ORR", "MOV", "BIC", "MVN"
-};
-
// check if the operand registers from a previous CMP or S-bit instruction
// would be overwritten by this instruction. If so, move the value to a
// safe register.
@@ -594,7 +591,7 @@
#endif
// multiply, accumulate
-void ArmToMips64Assembler::MLA(int cc, int s,
+void ArmToMips64Assembler::MLA(int cc __unused, int s,
int Rd, int Rm, int Rs, int Rn) {
//ALOGW("MLA");
@@ -608,7 +605,7 @@
}
}
-void ArmToMips64Assembler::MUL(int cc, int s,
+void ArmToMips64Assembler::MUL(int cc __unused, int s,
int Rd, int Rm, int Rs) {
mArmPC[mInum++] = pc();
mMips->MUL(Rd, Rm, Rs);
@@ -618,7 +615,7 @@
}
}
-void ArmToMips64Assembler::UMULL(int cc, int s,
+void ArmToMips64Assembler::UMULL(int cc __unused, int s,
int RdLo, int RdHi, int Rm, int Rs) {
mArmPC[mInum++] = pc();
mMips->MUH(RdHi, Rm, Rs);
@@ -631,8 +628,8 @@
}
}
-void ArmToMips64Assembler::UMUAL(int cc, int s,
- int RdLo, int RdHi, int Rm, int Rs) {
+void ArmToMips64Assembler::UMUAL(int cc __unused, int s,
+ int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
"UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
// *mPC++ = (cc<<28) | (1<<23) | (1<<21) | (s<<20) |
@@ -647,8 +644,8 @@
}
}
-void ArmToMips64Assembler::SMULL(int cc, int s,
- int RdLo, int RdHi, int Rm, int Rs) {
+void ArmToMips64Assembler::SMULL(int cc __unused, int s,
+ int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
"SMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
// *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (s<<20) |
@@ -662,8 +659,8 @@
LOG_ALWAYS_FATAL("Condition on SMULL must be on 64-bit result\n");
}
}
-void ArmToMips64Assembler::SMUAL(int cc, int s,
- int RdLo, int RdHi, int Rm, int Rs) {
+void ArmToMips64Assembler::SMUAL(int cc __unused, int s,
+ int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
"SMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
// *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (1<<21) | (s<<20) |
@@ -717,26 +714,26 @@
}
}
-void ArmToMips64Assembler::BL(int cc, const char* label)
+void ArmToMips64Assembler::BL(int cc __unused, const char* label __unused)
{
LOG_ALWAYS_FATAL("branch-and-link not supported yet\n");
mArmPC[mInum++] = pc();
}
// no use for Branches with integer PC, but they're in the Interface class ....
-void ArmToMips64Assembler::B(int cc, uint32_t* to_pc)
+void ArmToMips64Assembler::B(int cc __unused, uint32_t* to_pc __unused)
{
LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
mArmPC[mInum++] = pc();
}
-void ArmToMips64Assembler::BL(int cc, uint32_t* to_pc)
+void ArmToMips64Assembler::BL(int cc __unused, uint32_t* to_pc __unused)
{
LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
mArmPC[mInum++] = pc();
}
-void ArmToMips64Assembler::BX(int cc, int Rn)
+void ArmToMips64Assembler::BX(int cc __unused, int Rn __unused)
{
LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
mArmPC[mInum++] = pc();
@@ -750,7 +747,7 @@
#endif
// data transfer...
-void ArmToMips64Assembler::LDR(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMips64Assembler::LDR(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
@@ -784,7 +781,7 @@
}
}
-void ArmToMips64Assembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMips64Assembler::LDRB(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
@@ -813,7 +810,7 @@
}
-void ArmToMips64Assembler::STR(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMips64Assembler::STR(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
@@ -849,7 +846,7 @@
}
}
-void ArmToMips64Assembler::STRB(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMips64Assembler::STRB(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
@@ -877,7 +874,7 @@
}
}
-void ArmToMips64Assembler::LDRH(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMips64Assembler::LDRH(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed8_pre(0)
@@ -905,21 +902,23 @@
}
}
-void ArmToMips64Assembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMips64Assembler::LDRSB(int cc __unused, int Rd __unused,
+ int Rn __unused, uint32_t offset __unused)
{
mArmPC[mInum++] = pc();
mMips->NOP2();
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMips64Assembler::LDRSH(int cc __unused, int Rd __unused,
+ int Rn __unused, uint32_t offset __unused)
{
mArmPC[mInum++] = pc();
mMips->NOP2();
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::STRH(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMips64Assembler::STRH(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed8_pre(0)
@@ -955,8 +954,8 @@
#endif
// block data transfer...
-void ArmToMips64Assembler::LDM(int cc, int dir,
- int Rn, int W, uint32_t reg_list)
+void ArmToMips64Assembler::LDM(int cc __unused, int dir __unused,
+ int Rn __unused, int W __unused, uint32_t reg_list __unused)
{ // ED FD EA FA IB IA DB DA
// const uint8_t P[8] = { 1, 0, 1, 0, 1, 0, 1, 0 };
// const uint8_t U[8] = { 1, 1, 0, 0, 1, 1, 0, 0 };
@@ -967,8 +966,8 @@
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::STM(int cc, int dir,
- int Rn, int W, uint32_t reg_list)
+void ArmToMips64Assembler::STM(int cc __unused, int dir __unused,
+ int Rn __unused, int W __unused, uint32_t reg_list __unused)
{ // FA EA FD ED IB IA DB DA
// const uint8_t P[8] = { 0, 1, 0, 1, 1, 0, 1, 0 };
// const uint8_t U[8] = { 0, 0, 1, 1, 1, 1, 0, 0 };
@@ -987,21 +986,23 @@
#endif
// special...
-void ArmToMips64Assembler::SWP(int cc, int Rn, int Rd, int Rm) {
+void ArmToMips64Assembler::SWP(int cc __unused, int Rn __unused,
+ int Rd __unused, int Rm __unused) {
// *mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
mArmPC[mInum++] = pc();
mMips->NOP2();
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::SWPB(int cc, int Rn, int Rd, int Rm) {
+void ArmToMips64Assembler::SWPB(int cc __unused, int Rn __unused,
+ int Rd __unused, int Rm __unused) {
// *mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
mArmPC[mInum++] = pc();
mMips->NOP2();
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::SWI(int cc, uint32_t comment) {
+void ArmToMips64Assembler::SWI(int cc __unused, uint32_t comment __unused) {
// *mPC++ = (cc<<28) | (0xF<<24) | comment;
mArmPC[mInum++] = pc();
mMips->NOP2();
@@ -1015,7 +1016,7 @@
#endif
// DSP instructions...
-void ArmToMips64Assembler::PLD(int Rn, uint32_t offset) {
+void ArmToMips64Assembler::PLD(int Rn __unused, uint32_t offset) {
LOG_ALWAYS_FATAL_IF(!((offset&(1<<24)) && !(offset&(1<<21))),
"PLD only P=1, W=0");
// *mPC++ = 0xF550F000 | (Rn<<16) | offset;
@@ -1024,13 +1025,14 @@
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::CLZ(int cc, int Rd, int Rm)
+void ArmToMips64Assembler::CLZ(int cc __unused, int Rd, int Rm)
{
mArmPC[mInum++] = pc();
mMips->CLZ(Rd, Rm);
}
-void ArmToMips64Assembler::QADD(int cc, int Rd, int Rm, int Rn)
+void ArmToMips64Assembler::QADD(int cc __unused, int Rd __unused,
+ int Rm __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm;
mArmPC[mInum++] = pc();
@@ -1038,7 +1040,8 @@
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::QDADD(int cc, int Rd, int Rm, int Rn)
+void ArmToMips64Assembler::QDADD(int cc __unused, int Rd __unused,
+ int Rm __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm;
mArmPC[mInum++] = pc();
@@ -1046,7 +1049,8 @@
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::QSUB(int cc, int Rd, int Rm, int Rn)
+void ArmToMips64Assembler::QSUB(int cc __unused, int Rd __unused,
+ int Rm __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm;
mArmPC[mInum++] = pc();
@@ -1054,7 +1058,8 @@
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::QDSUB(int cc, int Rd, int Rm, int Rn)
+void ArmToMips64Assembler::QDSUB(int cc __unused, int Rd __unused,
+ int Rm __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm;
mArmPC[mInum++] = pc();
@@ -1063,7 +1068,7 @@
}
// 16 x 16 signed multiply (like SMLAxx without the accumulate)
-void ArmToMips64Assembler::SMUL(int cc, int xy,
+void ArmToMips64Assembler::SMUL(int cc __unused, int xy,
int Rd, int Rm, int Rs)
{
mArmPC[mInum++] = pc();
@@ -1092,7 +1097,7 @@
}
// signed 32b x 16b multiple, save top 32-bits of 48-bit result
-void ArmToMips64Assembler::SMULW(int cc, int y,
+void ArmToMips64Assembler::SMULW(int cc __unused, int y,
int Rd, int Rm, int Rs)
{
mArmPC[mInum++] = pc();
@@ -1111,7 +1116,7 @@
}
// 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn
-void ArmToMips64Assembler::SMLA(int cc, int xy,
+void ArmToMips64Assembler::SMLA(int cc __unused, int xy,
int Rd, int Rm, int Rs, int Rn)
{
mArmPC[mInum++] = pc();
@@ -1141,8 +1146,9 @@
mMips->ADDU(Rd, R_at, Rn);
}
-void ArmToMips64Assembler::SMLAL(int cc, int xy,
- int RdHi, int RdLo, int Rs, int Rm)
+void ArmToMips64Assembler::SMLAL(int cc __unused, int xy __unused,
+ int RdHi __unused, int RdLo __unused,
+ int Rs __unused, int Rm __unused)
{
// *mPC++ = (cc<<28) | 0x1400080 | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (xy<<4) | Rm;
mArmPC[mInum++] = pc();
@@ -1150,8 +1156,9 @@
NOT_IMPLEMENTED();
}
-void ArmToMips64Assembler::SMLAW(int cc, int y,
- int Rd, int Rm, int Rs, int Rn)
+void ArmToMips64Assembler::SMLAW(int cc __unused, int y __unused,
+ int Rd __unused, int Rm __unused,
+ int Rs __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm;
mArmPC[mInum++] = pc();
@@ -1160,7 +1167,7 @@
}
// used by ARMv6 version of GGLAssembler::filter32
-void ArmToMips64Assembler::UXTB16(int cc, int Rd, int Rm, int rotate)
+void ArmToMips64Assembler::UXTB16(int cc __unused, int Rd, int Rm, int rotate)
{
mArmPC[mInum++] = pc();
@@ -1173,7 +1180,8 @@
mMips->AND(Rd, R_at2, R_at);
}
-void ArmToMips64Assembler::UBFX(int cc, int Rd, int Rn, int lsb, int width)
+void ArmToMips64Assembler::UBFX(int cc __unused, int Rd __unused, int Rn __unused,
+ int lsb __unused, int width __unused)
{
/* Placeholder for UBFX */
mArmPC[mInum++] = pc();
@@ -1202,7 +1210,8 @@
dataProcessing(opSUB64, cc, s, Rd, Rn, Op2);
}
-void ArmToMips64Assembler::ADDR_LDR(int cc, int Rd, int Rn, uint32_t offset) {
+void ArmToMips64Assembler::ADDR_LDR(int cc __unused, int Rd,
+ int Rn, uint32_t offset) {
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
if (offset > AMODE_UNSUPPORTED) offset = 0;
@@ -1235,7 +1244,8 @@
}
}
-void ArmToMips64Assembler::ADDR_STR(int cc, int Rd, int Rn, uint32_t offset) {
+void ArmToMips64Assembler::ADDR_STR(int cc __unused, int Rd,
+ int Rn, uint32_t offset) {
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
if (offset > AMODE_UNSUPPORTED) offset = 0;
@@ -1290,14 +1300,12 @@
*/
MIPS64Assembler::MIPS64Assembler(const sp<Assembly>& assembly, ArmToMips64Assembler *parent)
- : mParent(parent),
- MIPSAssembler::MIPSAssembler(assembly, NULL)
+ : MIPSAssembler::MIPSAssembler(assembly, NULL), mParent(parent)
{
}
MIPS64Assembler::MIPS64Assembler(void* assembly, ArmToMips64Assembler *parent)
- : mParent(parent),
- MIPSAssembler::MIPSAssembler(assembly)
+ : MIPSAssembler::MIPSAssembler(assembly), mParent(parent)
{
}
@@ -1319,7 +1327,7 @@
}
-void MIPS64Assembler::disassemble(const char* name)
+void MIPS64Assembler::disassemble(const char* name __unused)
{
char di_buf[140];
@@ -1334,11 +1342,6 @@
}
}
- // iArm is an index to Arm instructions 1...n for this assembly sequence
- // mArmPC[iArm] holds the value of the Mips-PC for the first MIPS
- // instruction corresponding to that Arm instruction number
-
- int iArm = 0;
size_t count = pc()-base();
uint32_t* mipsPC = base();
diff --git a/libpixelflinger/codeflinger/MIPSAssembler.cpp b/libpixelflinger/codeflinger/MIPSAssembler.cpp
index 865a568..039a725 100644
--- a/libpixelflinger/codeflinger/MIPSAssembler.cpp
+++ b/libpixelflinger/codeflinger/MIPSAssembler.cpp
@@ -51,6 +51,7 @@
#include <stdio.h>
#include <stdlib.h>
+#include <inttypes.h>
#include <cutils/properties.h>
#include <log/log.h>
@@ -60,6 +61,8 @@
#include "MIPSAssembler.h"
#include "mips_disassem.h"
+#define __unused __attribute__((__unused__))
+
// Choose MIPS arch variant following gcc flags
#if defined(__mips__) && __mips==32 && __mips_isa_rev>=2
#define mips32r2 1
@@ -167,7 +170,7 @@
mMips->MOVE(R_v0, R_a0); // move context * passed in a0 to v0 (arm r0)
}
-void ArmToMipsAssembler::epilog(uint32_t touched)
+void ArmToMipsAssembler::epilog(uint32_t touched __unused)
{
mArmPC[mInum++] = pc(); // save starting PC for this instr
@@ -213,7 +216,7 @@
// shifters...
-bool ArmToMipsAssembler::isValidImmediate(uint32_t immediate)
+bool ArmToMipsAssembler::isValidImmediate(uint32_t immediate __unused)
{
// for MIPS, any 32-bit immediate is OK
return true;
@@ -234,13 +237,14 @@
return AMODE_REG_IMM;
}
-uint32_t ArmToMipsAssembler::reg_rrx(int Rm)
+uint32_t ArmToMipsAssembler::reg_rrx(int Rm __unused)
{
// reg_rrx mode is not used in the GLLAssember code at this time
return AMODE_UNSUPPORTED;
}
-uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs)
+uint32_t ArmToMipsAssembler::reg_reg(int Rm __unused, int type __unused,
+ int Rs __unused)
{
// reg_reg mode is not used in the GLLAssember code at this time
return AMODE_UNSUPPORTED;
@@ -281,14 +285,15 @@
return AMODE_REG_SCALE_PRE;
}
-uint32_t ArmToMipsAssembler::reg_scale_post(int Rm, int type, uint32_t shift)
+uint32_t ArmToMipsAssembler::reg_scale_post(int Rm __unused, int type __unused,
+ uint32_t shift __unused)
{
LOG_ALWAYS_FATAL("adr mode reg_scale_post not yet implemented\n");
return AMODE_UNSUPPORTED;
}
// LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
-uint32_t ArmToMipsAssembler::immed8_pre(int32_t immed8, int W)
+uint32_t ArmToMipsAssembler::immed8_pre(int32_t immed8, int W __unused)
{
// uint32_t offset = abs(immed8);
@@ -318,7 +323,7 @@
return AMODE_REG_PRE;
}
-uint32_t ArmToMipsAssembler::reg_post(int Rm)
+uint32_t ArmToMipsAssembler::reg_post(int Rm __unused)
{
LOG_ALWAYS_FATAL("adr mode reg_post not yet implemented\n");
return AMODE_UNSUPPORTED;
@@ -333,12 +338,6 @@
#pragma mark Data Processing...
#endif
-
-static const char * const dpOpNames[] = {
- "AND", "EOR", "SUB", "RSB", "ADD", "ADC", "SBC", "RSC",
- "TST", "TEQ", "CMP", "CMN", "ORR", "MOV", "BIC", "MVN"
-};
-
// check if the operand registers from a previous CMP or S-bit instruction
// would be overwritten by this instruction. If so, move the value to a
// safe register.
@@ -605,7 +604,7 @@
#endif
// multiply, accumulate
-void ArmToMipsAssembler::MLA(int cc, int s,
+void ArmToMipsAssembler::MLA(int cc __unused, int s,
int Rd, int Rm, int Rs, int Rn) {
mArmPC[mInum++] = pc(); // save starting PC for this instr
@@ -618,7 +617,7 @@
}
}
-void ArmToMipsAssembler::MUL(int cc, int s,
+void ArmToMipsAssembler::MUL(int cc __unused, int s,
int Rd, int Rm, int Rs) {
mArmPC[mInum++] = pc();
mMips->MUL(Rd, Rm, Rs);
@@ -628,7 +627,7 @@
}
}
-void ArmToMipsAssembler::UMULL(int cc, int s,
+void ArmToMipsAssembler::UMULL(int cc __unused, int s,
int RdLo, int RdHi, int Rm, int Rs) {
mArmPC[mInum++] = pc();
mMips->MULT(Rm, Rs);
@@ -641,8 +640,8 @@
}
}
-void ArmToMipsAssembler::UMUAL(int cc, int s,
- int RdLo, int RdHi, int Rm, int Rs) {
+void ArmToMipsAssembler::UMUAL(int cc __unused, int s,
+ int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
"UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
// *mPC++ = (cc<<28) | (1<<23) | (1<<21) | (s<<20) |
@@ -657,8 +656,8 @@
}
}
-void ArmToMipsAssembler::SMULL(int cc, int s,
- int RdLo, int RdHi, int Rm, int Rs) {
+void ArmToMipsAssembler::SMULL(int cc __unused, int s,
+ int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
"SMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
// *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (s<<20) |
@@ -672,8 +671,8 @@
LOG_ALWAYS_FATAL("Condition on SMULL must be on 64-bit result\n");
}
}
-void ArmToMipsAssembler::SMUAL(int cc, int s,
- int RdLo, int RdHi, int Rm, int Rs) {
+void ArmToMipsAssembler::SMUAL(int cc __unused, int s,
+ int RdLo __unused, int RdHi, int Rm __unused, int Rs __unused) {
LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
"SMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
// *mPC++ = (cc<<28) | (1<<23) | (1<<22) | (1<<21) | (s<<20) |
@@ -727,26 +726,26 @@
}
}
-void ArmToMipsAssembler::BL(int cc, const char* label)
+void ArmToMipsAssembler::BL(int cc __unused, const char* label __unused)
{
LOG_ALWAYS_FATAL("branch-and-link not supported yet\n");
mArmPC[mInum++] = pc();
}
// no use for Branches with integer PC, but they're in the Interface class ....
-void ArmToMipsAssembler::B(int cc, uint32_t* to_pc)
+void ArmToMipsAssembler::B(int cc __unused, uint32_t* to_pc __unused)
{
LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
mArmPC[mInum++] = pc();
}
-void ArmToMipsAssembler::BL(int cc, uint32_t* to_pc)
+void ArmToMipsAssembler::BL(int cc __unused, uint32_t* to_pc __unused)
{
LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
mArmPC[mInum++] = pc();
}
-void ArmToMipsAssembler::BX(int cc, int Rn)
+void ArmToMipsAssembler::BX(int cc __unused, int Rn __unused)
{
LOG_ALWAYS_FATAL("branch to absolute PC not supported, use Label\n");
mArmPC[mInum++] = pc();
@@ -760,7 +759,7 @@
#endif
// data transfer...
-void ArmToMipsAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMipsAssembler::LDR(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
@@ -794,7 +793,7 @@
}
}
-void ArmToMipsAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMipsAssembler::LDRB(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
@@ -823,7 +822,7 @@
}
-void ArmToMipsAssembler::STR(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMipsAssembler::STR(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
@@ -859,7 +858,7 @@
}
}
-void ArmToMipsAssembler::STRB(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMipsAssembler::STRB(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed12_pre(0)
@@ -887,7 +886,7 @@
}
}
-void ArmToMipsAssembler::LDRH(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMipsAssembler::LDRH(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed8_pre(0)
@@ -915,21 +914,23 @@
}
}
-void ArmToMipsAssembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMipsAssembler::LDRSB(int cc __unused, int Rd __unused,
+ int Rn __unused, uint32_t offset __unused)
{
mArmPC[mInum++] = pc();
mMips->NOP2();
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMipsAssembler::LDRSH(int cc __unused, int Rd __unused,
+ int Rn __unused, uint32_t offset __unused)
{
mArmPC[mInum++] = pc();
mMips->NOP2();
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::STRH(int cc, int Rd, int Rn, uint32_t offset)
+void ArmToMipsAssembler::STRH(int cc __unused, int Rd, int Rn, uint32_t offset)
{
mArmPC[mInum++] = pc();
// work-around for ARM default address mode of immed8_pre(0)
@@ -965,8 +966,8 @@
#endif
// block data transfer...
-void ArmToMipsAssembler::LDM(int cc, int dir,
- int Rn, int W, uint32_t reg_list)
+void ArmToMipsAssembler::LDM(int cc __unused, int dir __unused,
+ int Rn __unused, int W __unused, uint32_t reg_list __unused)
{ // ED FD EA FA IB IA DB DA
// const uint8_t P[8] = { 1, 0, 1, 0, 1, 0, 1, 0 };
// const uint8_t U[8] = { 1, 1, 0, 0, 1, 1, 0, 0 };
@@ -977,8 +978,8 @@
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::STM(int cc, int dir,
- int Rn, int W, uint32_t reg_list)
+void ArmToMipsAssembler::STM(int cc __unused, int dir __unused,
+ int Rn __unused, int W __unused, uint32_t reg_list __unused)
{ // FA EA FD ED IB IA DB DA
// const uint8_t P[8] = { 0, 1, 0, 1, 1, 0, 1, 0 };
// const uint8_t U[8] = { 0, 0, 1, 1, 1, 1, 0, 0 };
@@ -997,21 +998,23 @@
#endif
// special...
-void ArmToMipsAssembler::SWP(int cc, int Rn, int Rd, int Rm) {
+void ArmToMipsAssembler::SWP(int cc __unused, int Rn __unused,
+ int Rd __unused, int Rm __unused) {
// *mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
mArmPC[mInum++] = pc();
mMips->NOP2();
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::SWPB(int cc, int Rn, int Rd, int Rm) {
+void ArmToMipsAssembler::SWPB(int cc __unused, int Rn __unused,
+ int Rd __unused, int Rm __unused) {
// *mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
mArmPC[mInum++] = pc();
mMips->NOP2();
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::SWI(int cc, uint32_t comment) {
+void ArmToMipsAssembler::SWI(int cc __unused, uint32_t comment __unused) {
// *mPC++ = (cc<<28) | (0xF<<24) | comment;
mArmPC[mInum++] = pc();
mMips->NOP2();
@@ -1025,7 +1028,7 @@
#endif
// DSP instructions...
-void ArmToMipsAssembler::PLD(int Rn, uint32_t offset) {
+void ArmToMipsAssembler::PLD(int Rn __unused, uint32_t offset) {
LOG_ALWAYS_FATAL_IF(!((offset&(1<<24)) && !(offset&(1<<21))),
"PLD only P=1, W=0");
// *mPC++ = 0xF550F000 | (Rn<<16) | offset;
@@ -1034,13 +1037,14 @@
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::CLZ(int cc, int Rd, int Rm)
+void ArmToMipsAssembler::CLZ(int cc __unused, int Rd, int Rm)
{
mArmPC[mInum++] = pc();
mMips->CLZ(Rd, Rm);
}
-void ArmToMipsAssembler::QADD(int cc, int Rd, int Rm, int Rn)
+void ArmToMipsAssembler::QADD(int cc __unused, int Rd __unused,
+ int Rm __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm;
mArmPC[mInum++] = pc();
@@ -1048,7 +1052,8 @@
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::QDADD(int cc, int Rd, int Rm, int Rn)
+void ArmToMipsAssembler::QDADD(int cc __unused, int Rd __unused,
+ int Rm __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm;
mArmPC[mInum++] = pc();
@@ -1056,7 +1061,8 @@
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::QSUB(int cc, int Rd, int Rm, int Rn)
+void ArmToMipsAssembler::QSUB(int cc __unused, int Rd __unused,
+ int Rm __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm;
mArmPC[mInum++] = pc();
@@ -1064,7 +1070,8 @@
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::QDSUB(int cc, int Rd, int Rm, int Rn)
+void ArmToMipsAssembler::QDSUB(int cc __unused, int Rd __unused,
+ int Rm __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm;
mArmPC[mInum++] = pc();
@@ -1073,7 +1080,7 @@
}
// 16 x 16 signed multiply (like SMLAxx without the accumulate)
-void ArmToMipsAssembler::SMUL(int cc, int xy,
+void ArmToMipsAssembler::SMUL(int cc __unused, int xy,
int Rd, int Rm, int Rs)
{
mArmPC[mInum++] = pc();
@@ -1112,7 +1119,7 @@
}
// signed 32b x 16b multiple, save top 32-bits of 48-bit result
-void ArmToMipsAssembler::SMULW(int cc, int y,
+void ArmToMipsAssembler::SMULW(int cc __unused, int y,
int Rd, int Rm, int Rs)
{
mArmPC[mInum++] = pc();
@@ -1132,7 +1139,7 @@
}
// 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn
-void ArmToMipsAssembler::SMLA(int cc, int xy,
+void ArmToMipsAssembler::SMLA(int cc __unused, int xy,
int Rd, int Rm, int Rs, int Rn)
{
mArmPC[mInum++] = pc();
@@ -1172,8 +1179,9 @@
mMips->ADDU(Rd, R_at, Rn);
}
-void ArmToMipsAssembler::SMLAL(int cc, int xy,
- int RdHi, int RdLo, int Rs, int Rm)
+void ArmToMipsAssembler::SMLAL(int cc __unused, int xy __unused,
+ int RdHi __unused, int RdLo __unused,
+ int Rs __unused, int Rm __unused)
{
// *mPC++ = (cc<<28) | 0x1400080 | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (xy<<4) | Rm;
mArmPC[mInum++] = pc();
@@ -1181,8 +1189,9 @@
NOT_IMPLEMENTED();
}
-void ArmToMipsAssembler::SMLAW(int cc, int y,
- int Rd, int Rm, int Rs, int Rn)
+void ArmToMipsAssembler::SMLAW(int cc __unused, int y __unused,
+ int Rd __unused, int Rm __unused,
+ int Rs __unused, int Rn __unused)
{
// *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm;
mArmPC[mInum++] = pc();
@@ -1191,7 +1200,7 @@
}
// used by ARMv6 version of GGLAssembler::filter32
-void ArmToMipsAssembler::UXTB16(int cc, int Rd, int Rm, int rotate)
+void ArmToMipsAssembler::UXTB16(int cc __unused, int Rd, int Rm, int rotate)
{
mArmPC[mInum++] = pc();
@@ -1202,7 +1211,9 @@
mMips->AND(Rd, Rm, 0x00FF00FF);
}
-void ArmToMipsAssembler::UBFX(int cc, int Rd, int Rn, int lsb, int width)
+void ArmToMipsAssembler::UBFX(int cc __unused, int Rd __unused,
+ int Rn __unused, int lsb __unused,
+ int width __unused)
{
/* Placeholder for UBFX */
mArmPC[mInum++] = pc();
@@ -1339,11 +1350,6 @@
}
}
- // iArm is an index to Arm instructions 1...n for this assembly sequence
- // mArmPC[iArm] holds the value of the Mips-PC for the first MIPS
- // instruction corresponding to that Arm instruction number
-
- int iArm = 0;
size_t count = pc()-base();
uint32_t* mipsPC = base();
while (count--) {
@@ -1359,7 +1365,7 @@
::mips_disassem(mipsPC, di_buf, arm_disasm_fmt);
string_detab(di_buf);
string_pad(di_buf, 30);
- ALOGW("%08x: %08x %s", uintptr_t(mipsPC), uint32_t(*mipsPC), di_buf);
+ ALOGW("0x%p: %08x %s", mipsPC, uint32_t(*mipsPC), di_buf);
mipsPC++;
}
}
@@ -1381,7 +1387,7 @@
// empty - done in ArmToMipsAssembler
}
-void MIPSAssembler::epilog(uint32_t touched)
+void MIPSAssembler::epilog(uint32_t touched __unused)
{
// empty - done in ArmToMipsAssembler
}
@@ -1403,7 +1409,7 @@
// the instruction & data caches are flushed by CodeCache
const int64_t duration = ggl_system_time() - mDuration;
- const char * const format = "generated %s (%d ins) at [%p:%p] in %lld ns\n";
+ const char * const format = "generated %s (%d ins) at [%p:%p] in %" PRId64 " ns\n";
ALOGI(format, name, int(pc()-base()), base(), pc(), duration);
char value[PROPERTY_VALUE_MAX];
@@ -1864,7 +1870,7 @@
BEQ(Rs, R_zero, label);
}
-void MIPSAssembler::BNEZ(int Rs, const char* label)
+void MIPSAssembler::BNEZ(int Rs __unused, const char* label)
{
BNE(R_at, R_zero, label);
}
diff --git a/libpixelflinger/codeflinger/load_store.cpp b/libpixelflinger/codeflinger/load_store.cpp
index da21e1d..4db0a49 100644
--- a/libpixelflinger/codeflinger/load_store.cpp
+++ b/libpixelflinger/codeflinger/load_store.cpp
@@ -232,7 +232,6 @@
void GGLAssembler::downshift(
pixel_t& d, int component, component_t s, const reg_t& dither)
{
- const needs_t& needs = mBuilderContext.needs;
Scratch scratches(registerFile());
int sh = s.h;
diff --git a/libpixelflinger/codeflinger/mips64_disassem.c b/libpixelflinger/codeflinger/mips64_disassem.c
index 1856e5c..8528299 100644
--- a/libpixelflinger/codeflinger/mips64_disassem.c
+++ b/libpixelflinger/codeflinger/mips64_disassem.c
@@ -45,6 +45,8 @@
#include "mips_opcode.h"
+#define __unused __attribute__((__unused__))
+
static char *sprintf_buffer;
static int sprintf_buf_len;
@@ -114,7 +116,7 @@
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
-static char ** reg_name = &mips_reg_name[0];
+static char * const * reg_name = &mips_reg_name[0];
static const char * const c0_opname[64] = {
"c0op00","tlbr", "tlbwi", "c0op03","c0op04","c0op05","tlbwr", "c0op07",
@@ -147,7 +149,7 @@
* 'loc' may in fact contain a breakpoint instruction.
*/
static db_addr_t
-db_disasm_insn(int insn, db_addr_t loc, bool altfmt)
+db_disasm_insn(int insn, db_addr_t loc, bool altfmt __unused)
{
bool bdslot = false;
InstFmt i;
diff --git a/libpixelflinger/codeflinger/mips_disassem.c b/libpixelflinger/codeflinger/mips_disassem.c
index 83a9740..1fe6806 100644
--- a/libpixelflinger/codeflinger/mips_disassem.c
+++ b/libpixelflinger/codeflinger/mips_disassem.c
@@ -57,6 +57,7 @@
// #include <ddb/db_extern.h>
// #include <ddb/db_sym.h>
+#define __unused __attribute__((__unused__))
static char *sprintf_buffer;
static int sprintf_buf_len;
@@ -183,7 +184,7 @@
* 'loc' may in fact contain a breakpoint instruction.
*/
static db_addr_t
-db_disasm_insn(int insn, db_addr_t loc, bool altfmt)
+db_disasm_insn(int insn, db_addr_t loc, bool altfmt __unused)
{
bool bdslot = false;
InstFmt i;
diff --git a/libpixelflinger/codeflinger/texturing.cpp b/libpixelflinger/codeflinger/texturing.cpp
index 4c357af..e6997bd 100644
--- a/libpixelflinger/codeflinger/texturing.cpp
+++ b/libpixelflinger/codeflinger/texturing.cpp
@@ -41,7 +41,6 @@
void GGLAssembler::init_iterated_color(fragment_parts_t& parts, const reg_t& x)
{
context_t const* c = mBuilderContext.c;
- const needs_t& needs = mBuilderContext.needs;
if (mSmooth) {
// NOTE: we could take this case in the mDithering + !mSmooth case,
@@ -324,9 +323,7 @@
tex_coord_t* coords,
const reg_t& x, const reg_t& y)
{
- context_t const* c = mBuilderContext.c;
const needs_t& needs = mBuilderContext.needs;
- int Rctx = mBuilderContext.Rctx;
int Rx = x.reg;
int Ry = y.reg;
@@ -402,10 +399,6 @@
void GGLAssembler::build_textures( fragment_parts_t& parts,
Scratch& regs)
{
- context_t const* c = mBuilderContext.c;
- const needs_t& needs = mBuilderContext.needs;
- int Rctx = mBuilderContext.Rctx;
-
// We don't have a way to spill registers automatically
// spill depth and AA regs, when we know we may have to.
// build the spill list...
@@ -434,7 +427,6 @@
Spill spill(registerFile(), *this, spill_list);
- const bool multiTexture = mTextureMachine.activeUnits > 1;
for (int i=0 ; i<GGL_TEXTURE_UNIT_COUNT; i++) {
const texture_unit_t& tmu = mTextureMachine.tmu[i];
if (tmu.format_idx == 0)
@@ -442,7 +434,7 @@
pointer_t& txPtr = parts.coords[i].ptr;
pixel_t& texel = parts.texel[i];
-
+
// repeat...
if ((tmu.swrap == GGL_NEEDS_WRAP_11) &&
(tmu.twrap == GGL_NEEDS_WRAP_11))
@@ -656,7 +648,6 @@
void GGLAssembler::build_iterate_texture_coordinates(
const fragment_parts_t& parts)
{
- const bool multiTexture = mTextureMachine.activeUnits > 1;
for (int i=0 ; i<GGL_TEXTURE_UNIT_COUNT; i++) {
const texture_unit_t& tmu = mTextureMachine.tmu[i];
if (tmu.format_idx == 0)
diff --git a/libpixelflinger/include/private/pixelflinger/ggl_fixed.h b/libpixelflinger/include/private/pixelflinger/ggl_fixed.h
index 17b85dd..51e9e26 100644
--- a/libpixelflinger/include/private/pixelflinger/ggl_fixed.h
+++ b/libpixelflinger/include/private/pixelflinger/ggl_fixed.h
@@ -497,7 +497,6 @@
{
GGLfixed result;
- int rshift;
asm("smull %x[result], %w[x], %w[y] \n"
"lsr %x[result], %x[result], %x[shift] \n"
diff --git a/libpixelflinger/raster.cpp b/libpixelflinger/raster.cpp
index 26d8e45..e95c2c8 100644
--- a/libpixelflinger/raster.cpp
+++ b/libpixelflinger/raster.cpp
@@ -153,7 +153,6 @@
GGLint h = where[3];
// exclsively enable this tmu
- const GGLSurface& cbSurface = c->state.buffers.color.s;
c->procs.activeTexture(c, tmu);
c->procs.disable(c, GGL_W_LERP);
diff --git a/libpixelflinger/scanline.cpp b/libpixelflinger/scanline.cpp
index c6cf5bf..4cc23c7 100644
--- a/libpixelflinger/scanline.cpp
+++ b/libpixelflinger/scanline.cpp
@@ -2144,7 +2144,6 @@
const int32_t u = (c->state.texture[0].shade.is0>>16) + x;
const int32_t v = (c->state.texture[0].shade.it0>>16) + y;
uint32_t *src = reinterpret_cast<uint32_t*>(tex->data)+(u+(tex->stride*v));
- int sR, sG, sB;
uint32_t s, d;
if (ct==1 || uintptr_t(dst)&2) {
diff --git a/libpixelflinger/tests/arch-arm64/assembler/Android.mk b/libpixelflinger/tests/arch-arm64/assembler/Android.mk
index bd0f24b..db5dc4d 100644
--- a/libpixelflinger/tests/arch-arm64/assembler/Android.mk
+++ b/libpixelflinger/tests/arch-arm64/assembler/Android.mk
@@ -14,6 +14,8 @@
LOCAL_MODULE:= test-pixelflinger-arm64-assembler-test
+LOCAL_CFLAGS := -Wall -Werror
+
LOCAL_MODULE_TAGS := tests
LOCAL_MULTILIB := 64
diff --git a/libpixelflinger/tests/arch-arm64/col32cb16blend/Android.mk b/libpixelflinger/tests/arch-arm64/col32cb16blend/Android.mk
index 3368eb0..3096232 100644
--- a/libpixelflinger/tests/arch-arm64/col32cb16blend/Android.mk
+++ b/libpixelflinger/tests/arch-arm64/col32cb16blend/Android.mk
@@ -11,6 +11,8 @@
LOCAL_MODULE:= test-pixelflinger-arm64-col32cb16blend
+LOCAL_CFLAGS := -Wall -Werror
+
LOCAL_MODULE_TAGS := tests
LOCAL_MULTILIB := 64
diff --git a/libpixelflinger/tests/arch-arm64/disassembler/Android.mk b/libpixelflinger/tests/arch-arm64/disassembler/Android.mk
index d8f7e69..78f12af 100644
--- a/libpixelflinger/tests/arch-arm64/disassembler/Android.mk
+++ b/libpixelflinger/tests/arch-arm64/disassembler/Android.mk
@@ -9,6 +9,8 @@
LOCAL_MODULE:= test-pixelflinger-arm64-disassembler-test
+LOCAL_CFLAGS := -Wall -Werror
+
LOCAL_MODULE_TAGS := tests
LOCAL_MULTILIB := 64
diff --git a/libpixelflinger/tests/arch-arm64/t32cb16blend/Android.mk b/libpixelflinger/tests/arch-arm64/t32cb16blend/Android.mk
index 8e5ec5e..664347f 100644
--- a/libpixelflinger/tests/arch-arm64/t32cb16blend/Android.mk
+++ b/libpixelflinger/tests/arch-arm64/t32cb16blend/Android.mk
@@ -11,6 +11,8 @@
LOCAL_MODULE:= test-pixelflinger-arm64-t32cb16blend
+LOCAL_CFLAGS := -Wall -Werror
+
LOCAL_MODULE_TAGS := tests
LOCAL_MULTILIB := 64
diff --git a/libpixelflinger/tests/codegen/Android.mk b/libpixelflinger/tests/codegen/Android.mk
index 2f9ca2f..72d71ef 100644
--- a/libpixelflinger/tests/codegen/Android.mk
+++ b/libpixelflinger/tests/codegen/Android.mk
@@ -13,6 +13,8 @@
LOCAL_MODULE:= test-opengl-codegen
+LOCAL_CFLAGS:= -Wall -Werror
+
LOCAL_MODULE_TAGS := tests
include $(BUILD_NATIVE_TEST)
diff --git a/libpixelflinger/tests/codegen/codegen.cpp b/libpixelflinger/tests/codegen/codegen.cpp
index efa6d87..dce4ed7 100644
--- a/libpixelflinger/tests/codegen/codegen.cpp
+++ b/libpixelflinger/tests/codegen/codegen.cpp
@@ -40,9 +40,9 @@
const AssemblyKey<needs_t>& key() const { return mKey; }
};
+#if ANDROID_ARM_CODEGEN
static void ggl_test_codegen(uint32_t n, uint32_t p, uint32_t t0, uint32_t t1)
{
-#if ANDROID_ARM_CODEGEN
GGLContext* c;
gglInit(&c);
needs_t needs;
@@ -73,10 +73,12 @@
printf("error %08x (%s)\n", err, strerror(-err));
}
gglUninit(c);
-#else
- printf("This test runs only on ARM, Arm64 or MIPS\n");
-#endif
}
+#else
+static void ggl_test_codegen(uint32_t, uint32_t, uint32_t, uint32_t) {
+ printf("This test runs only on ARM, Arm64 or MIPS\n");
+}
+#endif
int main(int argc, char** argv)
{
diff --git a/libpixelflinger/tests/gglmul/Android.mk b/libpixelflinger/tests/gglmul/Android.mk
index 75bd39e..67f358f 100644
--- a/libpixelflinger/tests/gglmul/Android.mk
+++ b/libpixelflinger/tests/gglmul/Android.mk
@@ -11,6 +11,8 @@
LOCAL_MODULE:= test-pixelflinger-gglmul
+LOCAL_CFLAGS:= -Wall -Werror
+
LOCAL_MODULE_TAGS := tests
include $(BUILD_NATIVE_TEST)
diff --git a/libpixelflinger/trap.cpp b/libpixelflinger/trap.cpp
index 234bfdd..06ad237 100644
--- a/libpixelflinger/trap.cpp
+++ b/libpixelflinger/trap.cpp
@@ -349,7 +349,6 @@
static void linex(void *con, const GGLcoord* v0, const GGLcoord* v1, GGLcoord width)
{
- GGL_CONTEXT(c, con);
GGLcoord v[4][2];
v[0][0] = v0[0]; v[0][1] = v0[1];
v[1][0] = v1[0]; v[1][1] = v1[1];
@@ -377,7 +376,6 @@
static void aa_linex(void *con, const GGLcoord* v0, const GGLcoord* v1, GGLcoord width)
{
- GGL_CONTEXT(c, con);
GGLcoord v[4][2];
v[0][0] = v0[0]; v[0][1] = v0[1];
v[1][0] = v1[0]; v[1][1] = v1[1];
diff --git a/libunwindstack/DwarfSection.cpp b/libunwindstack/DwarfSection.cpp
index 2292168..91aef80 100644
--- a/libunwindstack/DwarfSection.cpp
+++ b/libunwindstack/DwarfSection.cpp
@@ -39,6 +39,10 @@
return nullptr;
}
const DwarfFde* fde = GetFdeFromOffset(fde_offset);
+ if (fde == nullptr) {
+ return nullptr;
+ }
+
// Guaranteed pc >= pc_start, need to check pc in the fde range.
if (pc < fde->pc_end) {
return fde;
diff --git a/libunwindstack/tests/DwarfEhFrameTest.cpp b/libunwindstack/tests/DwarfEhFrameTest.cpp
index 21114da..3dbabe1 100644
--- a/libunwindstack/tests/DwarfEhFrameTest.cpp
+++ b/libunwindstack/tests/DwarfEhFrameTest.cpp
@@ -399,13 +399,25 @@
EXPECT_EQ(0x20U, fde->cie->return_address_register);
}
+TYPED_TEST_P(DwarfEhFrameTest, GetFdeFromPc_fde_not_found) {
+ this->eh_frame_->TestSetTableEntrySize(16);
+ this->eh_frame_->TestSetFdeCount(1);
+
+ typename DwarfEhFrame<TypeParam>::FdeInfo info;
+ info.pc = 0x550;
+ info.offset = 0x10500;
+ this->eh_frame_->TestSetFdeInfo(0, info);
+
+ ASSERT_EQ(nullptr, this->eh_frame_->GetFdeFromPc(0x800));
+}
+
REGISTER_TYPED_TEST_CASE_P(DwarfEhFrameTest, Init, GetFdeInfoFromIndex_expect_cache_fail,
GetFdeInfoFromIndex_read_pcrel, GetFdeInfoFromIndex_read_datarel,
GetFdeInfoFromIndex_cached, GetFdeOffsetBinary_verify,
GetFdeOffsetSequential, GetFdeOffsetSequential_last_element,
GetFdeOffsetSequential_end_check, GetFdeOffsetFromPc_fail_fde_count,
GetFdeOffsetFromPc_binary_search, GetFdeOffsetFromPc_sequential_search,
- GetCieFde32, GetCieFde64);
+ GetCieFde32, GetCieFde64, GetFdeFromPc_fde_not_found);
typedef ::testing::Types<uint32_t, uint64_t> DwarfEhFrameTestTypes;
INSTANTIATE_TYPED_TEST_CASE_P(, DwarfEhFrameTest, DwarfEhFrameTestTypes);
diff --git a/toolbox/Android.mk b/toolbox/Android.mk
index 94029d8..c4795a7 100644
--- a/toolbox/Android.mk
+++ b/toolbox/Android.mk
@@ -59,3 +59,12 @@
$(INPUT_H_LABELS_H): $(LOCAL_PATH)/Android.mk $(LOCAL_PATH)/generate-input.h-labels.py $(UAPI_INPUT_EVENT_CODES_H)
$(INPUT_H_LABELS_H):
$(transform-generated-source)
+
+# We only want 'r' on userdebug and eng builds.
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES := r.c
+LOCAL_CFLAGS += $(common_cflags)
+LOCAL_C_INCLUDES += $(LOCAL_PATH)/upstream-netbsd/include/
+LOCAL_MODULE := r
+LOCAL_MODULE_TAGS := debug
+include $(BUILD_EXECUTABLE)
diff --git a/toolbox/r.c b/toolbox/r.c
new file mode 100644
index 0000000..b96cdb2
--- /dev/null
+++ b/toolbox/r.c
@@ -0,0 +1,102 @@
+#include <fcntl.h>
+#include <inttypes.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+
+#if __LP64__
+#define strtoptr strtoull
+#else
+#define strtoptr strtoul
+#endif
+
+static int usage()
+{
+ fprintf(stderr,"r [-b|-s] <address> [<value>]\n");
+ return -1;
+}
+
+int main(int argc, char *argv[])
+{
+ if(argc < 2) return usage();
+
+ int width = 4;
+ if(!strcmp(argv[1], "-b")) {
+ width = 1;
+ argc--;
+ argv++;
+ } else if(!strcmp(argv[1], "-s")) {
+ width = 2;
+ argc--;
+ argv++;
+ }
+
+ if(argc < 2) return usage();
+ uintptr_t addr = strtoptr(argv[1], 0, 16);
+
+ uintptr_t endaddr = 0;
+ char* end = strchr(argv[1], '-');
+ if (end)
+ endaddr = strtoptr(end + 1, 0, 16);
+
+ if (!endaddr)
+ endaddr = addr + width - 1;
+
+ if (endaddr <= addr) {
+ fprintf(stderr, "end address <= start address\n");
+ return -1;
+ }
+
+ bool set = false;
+ uint32_t value = 0;
+ if(argc > 2) {
+ set = true;
+ value = strtoul(argv[2], 0, 16);
+ }
+
+ int fd = open("/dev/mem", O_RDWR | O_SYNC);
+ if(fd < 0) {
+ fprintf(stderr,"cannot open /dev/mem\n");
+ return -1;
+ }
+
+ off64_t mmap_start = addr & ~(PAGE_SIZE - 1);
+ size_t mmap_size = endaddr - mmap_start + 1;
+ mmap_size = (mmap_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
+
+ void* page = mmap64(0, mmap_size, PROT_READ | PROT_WRITE,
+ MAP_SHARED, fd, mmap_start);
+
+ if(page == MAP_FAILED){
+ fprintf(stderr,"cannot mmap region\n");
+ return -1;
+ }
+
+ while (addr <= endaddr) {
+ switch(width){
+ case 4: {
+ uint32_t* x = (uint32_t*) (((uintptr_t) page) + (addr & 4095));
+ if(set) *x = value;
+ fprintf(stderr,"%08"PRIxPTR": %08x\n", addr, *x);
+ break;
+ }
+ case 2: {
+ uint16_t* x = (uint16_t*) (((uintptr_t) page) + (addr & 4095));
+ if(set) *x = value;
+ fprintf(stderr,"%08"PRIxPTR": %04x\n", addr, *x);
+ break;
+ }
+ case 1: {
+ uint8_t* x = (uint8_t*) (((uintptr_t) page) + (addr & 4095));
+ if(set) *x = value;
+ fprintf(stderr,"%08"PRIxPTR": %02x\n", addr, *x);
+ break;
+ }
+ }
+ addr += width;
+ }
+ return 0;
+}