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gerrit.omnirom.org / android_packages_modules_Virtualization / 196115bc1f614a76ab8d60c381834d32eda6ba34 / . / pvmfw / platform.dts
blob: e6ea2cc603f8216709e0ec011c1ba84a8be68f5b [file] [log] [blame]
Jiyong Park196115b2023-02-25 02:01:15 +0900[diff] [blame^]1/*
2 * Copyright (C) 2022 Google LLC
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6
7#define PLACEHOLDER 0xffffffff
8#define PLACEHOLDER2 PLACEHOLDER PLACEHOLDER
9#define PLACEHOLDER4 PLACEHOLDER2 PLACEHOLDER2
10
11/dts-v1/;
12
13/ {
14 interrupt-parent = <&intc>;
15 compatible = "linux,dummy-virt";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 chosen {
20 stdout-path = "/uart@3f8";
21 linux,pci-probe-only = <1>;
22 kaslr-seed = <PLACEHOLDER2>;
23 avf,strict-boot;
24 avf,new-instance;
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x00 CONFIG_SYS_SDRAM_BASE PLACEHOLDER2>;
30 };
31
32 reserved-memory {
33 #address-cells = <2>;
34 #size-cells = <2>;
35 ranges;
36 swiotlb: restricted_dma_reserved {
37 compatible = "restricted-dma-pool";
38 size = <PLACEHOLDER2>;
39 alignment = <PLACEHOLDER2>;
40 };
41
42 dice {
43 compatible = "google,open-dice";
44 no-map;
45 reg = <PLACEHOLDER4>;
46 };
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,arm-v8";
55 enable-method = "psci";
56 reg = <0>;
57 };
58 cpu@1 {
59 device_type = "cpu";
60 compatible = "arm,arm-v8";
61 enable-method = "psci";
62 reg = <1>;
63 };
64 cpu@2 {
65 device_type = "cpu";
66 compatible = "arm,arm-v8";
67 enable-method = "psci";
68 reg = <2>;
69 };
70 cpu@3 {
71 device_type = "cpu";
72 compatible = "arm,arm-v8";
73 enable-method = "psci";
74 reg = <3>;
75 };
76 cpu@4 {
77 device_type = "cpu";
78 compatible = "arm,arm-v8";
79 enable-method = "psci";
80 reg = <4>;
81 };
82 cpu@5 {
83 device_type = "cpu";
84 compatible = "arm,arm-v8";
85 enable-method = "psci";
86 reg = <5>;
87 };
88 cpu@6 {
89 device_type = "cpu";
90 compatible = "arm,arm-v8";
91 enable-method = "psci";
92 reg = <6>;
93 };
94 cpu@7 {
95 device_type = "cpu";
96 compatible = "arm,arm-v8";
97 enable-method = "psci";
98 reg = <7>;
99 };
100 cpu@8 {
101 device_type = "cpu";
102 compatible = "arm,arm-v8";
103 enable-method = "psci";
104 reg = <8>;
105 };
106 cpu@9 {
107 device_type = "cpu";
108 compatible = "arm,arm-v8";
109 enable-method = "psci";
110 reg = <9>;
111 };
112 cpu@10 {
113 device_type = "cpu";
114 compatible = "arm,arm-v8";
115 enable-method = "psci";
116 reg = <10>;
117 };
118 cpu@11 {
119 device_type = "cpu";
120 compatible = "arm,arm-v8";
121 enable-method = "psci";
122 reg = <11>;
123 };
124 cpu@12 {
125 device_type = "cpu";
126 compatible = "arm,arm-v8";
127 enable-method = "psci";
128 reg = <12>;
129 };
130 cpu@13 {
131 device_type = "cpu";
132 compatible = "arm,arm-v8";
133 enable-method = "psci";
134 reg = <13>;
135 };
136 cpu@14 {
137 device_type = "cpu";
138 compatible = "arm,arm-v8";
139 enable-method = "psci";
140 reg = <14>;
141 };
142 cpu@15 {
143 device_type = "cpu";
144 compatible = "arm,arm-v8";
145 enable-method = "psci";
146 reg = <15>;
147 };
148 };
149
150 intc: intc {
151 compatible = "arm,gic-v3";
152 #address-cells = <2>;
153 #size-cells = <2>;
154 #interrupt-cells = <3>;
155 interrupt-controller;
156 reg = <0x00 0x3fff0000 0x00 0x10000>, <PLACEHOLDER4>;
157 };
158
159 timer {
160 compatible = "arm,armv8-timer";
161 always-on;
162 /* The IRQ type needs to be OR-ed with the CPU mask */
163 interrupts = <GIC_PPI 0xd IRQ_TYPE_LEVEL_LOW
164 GIC_PPI 0xe IRQ_TYPE_LEVEL_LOW
165 GIC_PPI 0xb IRQ_TYPE_LEVEL_LOW
166 GIC_PPI 0xa IRQ_TYPE_LEVEL_LOW>;
167 };
168
169 uart@2e8 {
170 compatible = "ns16550a";
171 reg = <0x00 0x2e8 0x00 0x8>;
172 clock-frequency = <0x1c2000>;
173 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
174 };
175
176 uart@2f8 {
177 compatible = "ns16550a";
178 reg = <0x00 0x2f8 0x00 0x8>;
179 clock-frequency = <0x1c2000>;
180 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
181 };
182
183 uart@3e8 {
184 compatible = "ns16550a";
185 reg = <0x00 0x3e8 0x00 0x8>;
186 clock-frequency = <0x1c2000>;
187 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
188 };
189
190 uart@3f8 {
191 compatible = "ns16550a";
192 reg = <0x00 0x3f8 0x00 0x8>;
193 clock-frequency = <0x1c2000>;
194 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
195 };
196
197 psci {
198 compatible = "arm,psci-1.0";
199 method = "hvc";
200 };
201
202 pci {
203 compatible = "pci-host-cam-generic";
204 device_type = "pci";
205 #address-cells = <3>;
206 #size-cells = <2>;
207 #interrupt-cells = <1>;
208 dma-coherent;
209 memory-region = <&swiotlb>;
210 ranges = <
211 0x3000000 0x0 0x02000000 0x0 0x02000000 0x00 0x02000000
212 0x3000000 PLACEHOLDER2 PLACEHOLDER2 PLACEHOLDER2
213 >;
214 bus-range = <0x00 0x00>;
215 reg = <0x00 0x10000 0x00 0x1000000>;
216 interrupt-map = <
217 0x0800 0x0 0x0 1 &intc 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
218 0x1000 0x0 0x0 1 &intc 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
219 0x1800 0x0 0x0 1 &intc 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
220 0x2000 0x0 0x0 1 &intc 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
221 0x2800 0x0 0x0 1 &intc 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
222 0x3000 0x0 0x0 1 &intc 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
223 0x3800 0x0 0x0 1 &intc 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
224 >;
225 interrupt-map-mask = <0xf800 0x0 0x0 0x7
226 0xf800 0x0 0x0 0x7
227 0xf800 0x0 0x0 0x7
228 0xf800 0x0 0x0 0x7
229 0xf800 0x0 0x0 0x7
230 0xf800 0x0 0x0 0x7
231 0xf800 0x0 0x0 0x7>;
232 };
233
234 clk: pclk@3M {
235 compatible = "fixed-clock";
236 clock-frequency = <0x2fefd8>;
237 #clock-cells = <0>;
238 };
239
240 rtc@2000 {
241 compatible = "arm,primecell";
242 arm,primecell-periphid = <0x41030>;
243 reg = <0x00 0x2000 0x00 0x1000>;
244 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
245 clock-names = "apb_pclk";
246 clocks = <&clk>;
247 };
248};