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Pierre-Clément Tosia0934c12022-11-25 20:54:11 +00001// Copyright 2022, The Android Open Source Project
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15//! High-level FDT functions.
16
Jiyong Parkc5d2ef22023-04-11 01:23:46 +090017use crate::bootargs::BootArgsIterator;
Jiyong Parkb87f3302023-03-21 10:03:11 +090018use crate::cstr;
Pierre-Clément Tosife6e47c2023-04-28 13:12:07 +000019use crate::helpers::RangeExt as _;
Jiyong Park00ceff32023-03-13 05:43:23 +000020use crate::helpers::GUEST_PAGE_SIZE;
Jiyong Park0ee65392023-03-27 20:52:45 +090021use crate::memory::BASE_ADDR;
22use crate::memory::MAX_ADDR;
Jiyong Parkc5d2ef22023-04-11 01:23:46 +090023use crate::Box;
Jiyong Park00ceff32023-03-13 05:43:23 +000024use crate::RebootReason;
Jiyong Parke9d87e82023-03-21 19:28:40 +090025use alloc::ffi::CString;
Jiyong Parkc23426b2023-04-10 17:32:27 +090026use alloc::vec::Vec;
Jiyong Park0ee65392023-03-27 20:52:45 +090027use core::cmp::max;
28use core::cmp::min;
Pierre-Clément Tosia0934c12022-11-25 20:54:11 +000029use core::ffi::CStr;
Jiyong Park9c63cd12023-03-21 17:53:07 +090030use core::mem::size_of;
Pierre-Clément Tosia0934c12022-11-25 20:54:11 +000031use core::ops::Range;
Jiyong Park00ceff32023-03-13 05:43:23 +000032use fdtpci::PciMemoryFlags;
33use fdtpci::PciRangeType;
34use libfdt::AddressRange;
35use libfdt::CellIterator;
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +000036use libfdt::Fdt;
37use libfdt::FdtError;
Jiyong Park9c63cd12023-03-21 17:53:07 +090038use libfdt::FdtNode;
Jiyong Park83316122023-03-21 09:39:39 +090039use log::debug;
Jiyong Park00ceff32023-03-13 05:43:23 +000040use log::error;
Jiyong Parkc23426b2023-04-10 17:32:27 +090041use log::info;
Pierre-Clément Tosia50167b2023-05-02 13:19:29 +000042use log::warn;
Jiyong Park00ceff32023-03-13 05:43:23 +000043use tinyvec::ArrayVec;
Alice Wangeacb7382023-06-05 12:53:54 +000044use vmbase::memory::SIZE_4KB;
45use vmbase::util::flatten;
Pierre-Clément Tosia0934c12022-11-25 20:54:11 +000046
Jiyong Park6a8789a2023-03-21 14:50:59 +090047/// Extract from /config the address range containing the pre-loaded kernel. Absence of /config is
48/// not an error.
49fn read_kernel_range_from(fdt: &Fdt) -> libfdt::Result<Option<Range<usize>>> {
Jiyong Parkb87f3302023-03-21 10:03:11 +090050 let addr = cstr!("kernel-address");
51 let size = cstr!("kernel-size");
Pierre-Clément Tosic3811b82022-11-29 11:24:16 +000052
Jiyong Parkb87f3302023-03-21 10:03:11 +090053 if let Some(config) = fdt.node(cstr!("/config"))? {
Pierre-Clément Tosic3811b82022-11-29 11:24:16 +000054 if let (Some(addr), Some(size)) = (config.getprop_u32(addr)?, config.getprop_u32(size)?) {
55 let addr = addr as usize;
56 let size = size as usize;
57
58 return Ok(Some(addr..(addr + size)));
59 }
60 }
61
62 Ok(None)
63}
64
Jiyong Park6a8789a2023-03-21 14:50:59 +090065/// Extract from /chosen the address range containing the pre-loaded ramdisk. Absence is not an
66/// error as there can be initrd-less VM.
67fn read_initrd_range_from(fdt: &Fdt) -> libfdt::Result<Option<Range<usize>>> {
Jiyong Parkb87f3302023-03-21 10:03:11 +090068 let start = cstr!("linux,initrd-start");
69 let end = cstr!("linux,initrd-end");
Pierre-Clément Tosia0934c12022-11-25 20:54:11 +000070
71 if let Some(chosen) = fdt.chosen()? {
72 if let (Some(start), Some(end)) = (chosen.getprop_u32(start)?, chosen.getprop_u32(end)?) {
73 return Ok(Some((start as usize)..(end as usize)));
74 }
75 }
76
77 Ok(None)
78}
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +000079
Jiyong Park9c63cd12023-03-21 17:53:07 +090080fn patch_initrd_range(fdt: &mut Fdt, initrd_range: &Range<usize>) -> libfdt::Result<()> {
81 let start = u32::try_from(initrd_range.start).unwrap();
82 let end = u32::try_from(initrd_range.end).unwrap();
83
84 let mut node = fdt.chosen_mut()?.ok_or(FdtError::NotFound)?;
85 node.setprop(cstr!("linux,initrd-start"), &start.to_be_bytes())?;
86 node.setprop(cstr!("linux,initrd-end"), &end.to_be_bytes())?;
87 Ok(())
88}
89
Jiyong Parke9d87e82023-03-21 19:28:40 +090090fn read_bootargs_from(fdt: &Fdt) -> libfdt::Result<Option<CString>> {
91 if let Some(chosen) = fdt.chosen()? {
92 if let Some(bootargs) = chosen.getprop_str(cstr!("bootargs"))? {
93 // We need to copy the string to heap because the original fdt will be invalidated
94 // by the templated DT
95 let copy = CString::new(bootargs.to_bytes()).map_err(|_| FdtError::BadValue)?;
96 return Ok(Some(copy));
97 }
98 }
99 Ok(None)
100}
101
102fn patch_bootargs(fdt: &mut Fdt, bootargs: &CStr) -> libfdt::Result<()> {
103 let mut node = fdt.chosen_mut()?.ok_or(FdtError::NotFound)?;
Jiyong Parkc5d2ef22023-04-11 01:23:46 +0900104 // This function is called before the verification is done. So, we just copy the bootargs to
105 // the new FDT unmodified. This will be filtered again in the modify_for_next_stage function
106 // if the VM is not debuggable.
Jiyong Parke9d87e82023-03-21 19:28:40 +0900107 node.setprop(cstr!("bootargs"), bootargs.to_bytes_with_nul())
108}
109
Jiyong Park6a8789a2023-03-21 14:50:59 +0900110/// Read the first range in /memory node in DT
111fn read_memory_range_from(fdt: &Fdt) -> libfdt::Result<Range<usize>> {
112 fdt.memory()?.ok_or(FdtError::NotFound)?.next().ok_or(FdtError::NotFound)
113}
Jiyong Park00ceff32023-03-13 05:43:23 +0000114
Jiyong Park6a8789a2023-03-21 14:50:59 +0900115/// Check if memory range is ok
116fn validate_memory_range(range: &Range<usize>) -> Result<(), RebootReason> {
117 let base = range.start;
Jiyong Park0ee65392023-03-27 20:52:45 +0900118 if base != BASE_ADDR {
119 error!("Memory base address {:#x} is not {:#x}", base, BASE_ADDR);
Jiyong Park00ceff32023-03-13 05:43:23 +0000120 return Err(RebootReason::InvalidFdt);
121 }
122
Jiyong Park6a8789a2023-03-21 14:50:59 +0900123 let size = range.len();
Jiyong Park00ceff32023-03-13 05:43:23 +0000124 if size % GUEST_PAGE_SIZE != 0 {
125 error!("Memory size {:#x} is not a multiple of page size {:#x}", size, GUEST_PAGE_SIZE);
126 return Err(RebootReason::InvalidFdt);
127 }
Jiyong Park00ceff32023-03-13 05:43:23 +0000128
Jiyong Park6a8789a2023-03-21 14:50:59 +0900129 if size == 0 {
130 error!("Memory size is 0");
131 return Err(RebootReason::InvalidFdt);
132 }
133 Ok(())
Jiyong Park00ceff32023-03-13 05:43:23 +0000134}
135
Jiyong Park9c63cd12023-03-21 17:53:07 +0900136fn patch_memory_range(fdt: &mut Fdt, memory_range: &Range<usize>) -> libfdt::Result<()> {
137 let size = memory_range.len() as u64;
Jiyong Park0ee65392023-03-27 20:52:45 +0900138 fdt.node_mut(cstr!("/memory"))?
139 .ok_or(FdtError::NotFound)?
140 .setprop_inplace(cstr!("reg"), flatten(&[BASE_ADDR.to_be_bytes(), size.to_be_bytes()]))
Jiyong Park9c63cd12023-03-21 17:53:07 +0900141}
142
Jiyong Park6a8789a2023-03-21 14:50:59 +0900143/// Read the number of CPUs from DT
144fn read_num_cpus_from(fdt: &Fdt) -> libfdt::Result<usize> {
145 Ok(fdt.compatible_nodes(cstr!("arm,arm-v8"))?.count())
146}
147
148/// Validate number of CPUs
149fn validate_num_cpus(num_cpus: usize) -> Result<(), RebootReason> {
150 if num_cpus == 0 {
Jiyong Park00ceff32023-03-13 05:43:23 +0000151 error!("Number of CPU can't be 0");
Jiyong Park6a8789a2023-03-21 14:50:59 +0900152 return Err(RebootReason::InvalidFdt);
153 }
Jiyong Park9c63cd12023-03-21 17:53:07 +0900154 if DeviceTreeInfo::GIC_REDIST_SIZE_PER_CPU.checked_mul(num_cpus.try_into().unwrap()).is_none() {
155 error!("Too many CPUs for gic: {}", num_cpus);
156 return Err(RebootReason::InvalidFdt);
157 }
158 Ok(())
159}
160
161/// Patch DT by keeping `num_cpus` number of arm,arm-v8 compatible nodes, and pruning the rest.
162fn patch_num_cpus(fdt: &mut Fdt, num_cpus: usize) -> libfdt::Result<()> {
163 let cpu = cstr!("arm,arm-v8");
164 let mut next = fdt.root_mut()?.next_compatible(cpu)?;
165 for _ in 0..num_cpus {
166 next = if let Some(current) = next {
167 current.next_compatible(cpu)?
168 } else {
169 return Err(FdtError::NoSpace);
170 };
171 }
172 while let Some(current) = next {
173 next = current.delete_and_next_compatible(cpu)?;
174 }
Jiyong Park6a8789a2023-03-21 14:50:59 +0900175 Ok(())
Jiyong Park00ceff32023-03-13 05:43:23 +0000176}
177
178#[derive(Debug)]
Jiyong Park00ceff32023-03-13 05:43:23 +0000179struct PciInfo {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900180 ranges: [PciAddrRange; 2],
181 irq_masks: ArrayVec<[PciIrqMask; PciInfo::MAX_IRQS]>,
182 irq_maps: ArrayVec<[PciIrqMap; PciInfo::MAX_IRQS]>,
Jiyong Park00ceff32023-03-13 05:43:23 +0000183}
184
Jiyong Park6a8789a2023-03-21 14:50:59 +0900185impl PciInfo {
186 const IRQ_MASK_CELLS: usize = 4;
187 const IRQ_MAP_CELLS: usize = 10;
188 const MAX_IRQS: usize = 8;
Jiyong Park00ceff32023-03-13 05:43:23 +0000189}
190
Jiyong Park6a8789a2023-03-21 14:50:59 +0900191type PciAddrRange = AddressRange<(u32, u64), u64, u64>;
192type PciIrqMask = [u32; PciInfo::IRQ_MASK_CELLS];
193type PciIrqMap = [u32; PciInfo::IRQ_MAP_CELLS];
Jiyong Park00ceff32023-03-13 05:43:23 +0000194
195/// Iterator that takes N cells as a chunk
196struct CellChunkIterator<'a, const N: usize> {
197 cells: CellIterator<'a>,
198}
199
200impl<'a, const N: usize> CellChunkIterator<'a, N> {
201 fn new(cells: CellIterator<'a>) -> Self {
202 Self { cells }
203 }
204}
205
206impl<'a, const N: usize> Iterator for CellChunkIterator<'a, N> {
207 type Item = [u32; N];
208 fn next(&mut self) -> Option<Self::Item> {
209 let mut ret: Self::Item = [0; N];
210 for i in ret.iter_mut() {
211 *i = self.cells.next()?;
212 }
213 Some(ret)
214 }
215}
216
Jiyong Park6a8789a2023-03-21 14:50:59 +0900217/// Read pci host controller ranges, irq maps, and irq map masks from DT
218fn read_pci_info_from(fdt: &Fdt) -> libfdt::Result<PciInfo> {
219 let node =
220 fdt.compatible_nodes(cstr!("pci-host-cam-generic"))?.next().ok_or(FdtError::NotFound)?;
221
222 let mut ranges = node.ranges::<(u32, u64), u64, u64>()?.ok_or(FdtError::NotFound)?;
223 let range0 = ranges.next().ok_or(FdtError::NotFound)?;
224 let range1 = ranges.next().ok_or(FdtError::NotFound)?;
225
226 let irq_masks = node.getprop_cells(cstr!("interrupt-map-mask"))?.ok_or(FdtError::NotFound)?;
227 let irq_masks = CellChunkIterator::<{ PciInfo::IRQ_MASK_CELLS }>::new(irq_masks);
228 let irq_masks: ArrayVec<[PciIrqMask; PciInfo::MAX_IRQS]> =
229 irq_masks.take(PciInfo::MAX_IRQS).collect();
230
231 let irq_maps = node.getprop_cells(cstr!("interrupt-map"))?.ok_or(FdtError::NotFound)?;
232 let irq_maps = CellChunkIterator::<{ PciInfo::IRQ_MAP_CELLS }>::new(irq_maps);
233 let irq_maps: ArrayVec<[PciIrqMap; PciInfo::MAX_IRQS]> =
234 irq_maps.take(PciInfo::MAX_IRQS).collect();
235
236 Ok(PciInfo { ranges: [range0, range1], irq_masks, irq_maps })
237}
238
Jiyong Park0ee65392023-03-27 20:52:45 +0900239fn validate_pci_info(pci_info: &PciInfo, memory_range: &Range<usize>) -> Result<(), RebootReason> {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900240 for range in pci_info.ranges.iter() {
Jiyong Park0ee65392023-03-27 20:52:45 +0900241 validate_pci_addr_range(range, memory_range)?;
Jiyong Park6a8789a2023-03-21 14:50:59 +0900242 }
243 for irq_mask in pci_info.irq_masks.iter() {
244 validate_pci_irq_mask(irq_mask)?;
245 }
246 for (idx, irq_map) in pci_info.irq_maps.iter().enumerate() {
247 validate_pci_irq_map(irq_map, idx)?;
248 }
249 Ok(())
250}
251
Jiyong Park0ee65392023-03-27 20:52:45 +0900252fn validate_pci_addr_range(
253 range: &PciAddrRange,
254 memory_range: &Range<usize>,
255) -> Result<(), RebootReason> {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900256 let mem_flags = PciMemoryFlags(range.addr.0);
257 let range_type = mem_flags.range_type();
258 let prefetchable = mem_flags.prefetchable();
259 let bus_addr = range.addr.1;
260 let cpu_addr = range.parent_addr;
261 let size = range.size;
262
263 if range_type != PciRangeType::Memory64 {
264 error!("Invalid range type {:?} for bus address {:#x} in PCI node", range_type, bus_addr);
265 return Err(RebootReason::InvalidFdt);
266 }
267 if prefetchable {
268 error!("PCI bus address {:#x} in PCI node is prefetchable", bus_addr);
269 return Err(RebootReason::InvalidFdt);
270 }
271 // Enforce ID bus-to-cpu mappings, as used by crosvm.
272 if bus_addr != cpu_addr {
273 error!("PCI bus address: {:#x} is different from CPU address: {:#x}", bus_addr, cpu_addr);
274 return Err(RebootReason::InvalidFdt);
275 }
276
Jiyong Park0ee65392023-03-27 20:52:45 +0900277 let Some(bus_end) = bus_addr.checked_add(size) else {
278 error!("PCI address range size {:#x} overflows", size);
279 return Err(RebootReason::InvalidFdt);
280 };
281 if bus_end > MAX_ADDR.try_into().unwrap() {
282 error!("PCI address end {:#x} is outside of translatable range", bus_end);
283 return Err(RebootReason::InvalidFdt);
284 }
285
286 let memory_start = memory_range.start.try_into().unwrap();
287 let memory_end = memory_range.end.try_into().unwrap();
288
289 if max(bus_addr, memory_start) < min(bus_end, memory_end) {
290 error!(
291 "PCI address range {:#x}-{:#x} overlaps with main memory range {:#x}-{:#x}",
292 bus_addr, bus_end, memory_start, memory_end
293 );
Jiyong Park6a8789a2023-03-21 14:50:59 +0900294 return Err(RebootReason::InvalidFdt);
295 }
296
297 Ok(())
298}
299
300fn validate_pci_irq_mask(irq_mask: &PciIrqMask) -> Result<(), RebootReason> {
Jiyong Park00ceff32023-03-13 05:43:23 +0000301 const IRQ_MASK_ADDR_HI: u32 = 0xf800;
302 const IRQ_MASK_ADDR_ME: u32 = 0x0;
303 const IRQ_MASK_ADDR_LO: u32 = 0x0;
304 const IRQ_MASK_ANY_IRQ: u32 = 0x7;
Jiyong Park6a8789a2023-03-21 14:50:59 +0900305 const EXPECTED: PciIrqMask =
Jiyong Park00ceff32023-03-13 05:43:23 +0000306 [IRQ_MASK_ADDR_HI, IRQ_MASK_ADDR_ME, IRQ_MASK_ADDR_LO, IRQ_MASK_ANY_IRQ];
Jiyong Park6a8789a2023-03-21 14:50:59 +0900307 if *irq_mask != EXPECTED {
308 error!("Invalid PCI irq mask {:#?}", irq_mask);
309 return Err(RebootReason::InvalidFdt);
Jiyong Park00ceff32023-03-13 05:43:23 +0000310 }
Jiyong Park6a8789a2023-03-21 14:50:59 +0900311 Ok(())
Jiyong Park00ceff32023-03-13 05:43:23 +0000312}
313
Jiyong Park6a8789a2023-03-21 14:50:59 +0900314fn validate_pci_irq_map(irq_map: &PciIrqMap, idx: usize) -> Result<(), RebootReason> {
Jiyong Park00ceff32023-03-13 05:43:23 +0000315 const PCI_DEVICE_IDX: usize = 11;
316 const PCI_IRQ_ADDR_ME: u32 = 0;
317 const PCI_IRQ_ADDR_LO: u32 = 0;
318 const PCI_IRQ_INTC: u32 = 1;
319 const AARCH64_IRQ_BASE: u32 = 4; // from external/crosvm/aarch64/src/lib.rs
320 const GIC_SPI: u32 = 0;
321 const IRQ_TYPE_LEVEL_HIGH: u32 = 4;
322
Jiyong Park6a8789a2023-03-21 14:50:59 +0900323 let pci_addr = (irq_map[0], irq_map[1], irq_map[2]);
324 let pci_irq_number = irq_map[3];
325 let _controller_phandle = irq_map[4]; // skipped.
326 let gic_addr = (irq_map[5], irq_map[6]); // address-cells is <2> for GIC
327 // interrupt-cells is <3> for GIC
328 let gic_peripheral_interrupt_type = irq_map[7];
329 let gic_irq_number = irq_map[8];
330 let gic_irq_type = irq_map[9];
Jiyong Park00ceff32023-03-13 05:43:23 +0000331
Jiyong Park6a8789a2023-03-21 14:50:59 +0900332 let phys_hi: u32 = (0x1 << PCI_DEVICE_IDX) * (idx + 1) as u32;
333 let expected_pci_addr = (phys_hi, PCI_IRQ_ADDR_ME, PCI_IRQ_ADDR_LO);
Jiyong Park00ceff32023-03-13 05:43:23 +0000334
Jiyong Park6a8789a2023-03-21 14:50:59 +0900335 if pci_addr != expected_pci_addr {
336 error!("PCI device address {:#x} {:#x} {:#x} in interrupt-map is different from expected address \
337 {:#x} {:#x} {:#x}",
338 pci_addr.0, pci_addr.1, pci_addr.2, expected_pci_addr.0, expected_pci_addr.1, expected_pci_addr.2);
339 return Err(RebootReason::InvalidFdt);
340 }
Jiyong Park00ceff32023-03-13 05:43:23 +0000341
Jiyong Park6a8789a2023-03-21 14:50:59 +0900342 if pci_irq_number != PCI_IRQ_INTC {
343 error!(
344 "PCI INT# {:#x} in interrupt-map is different from expected value {:#x}",
345 pci_irq_number, PCI_IRQ_INTC
346 );
347 return Err(RebootReason::InvalidFdt);
348 }
Jiyong Park00ceff32023-03-13 05:43:23 +0000349
Jiyong Park6a8789a2023-03-21 14:50:59 +0900350 if gic_addr != (0, 0) {
351 error!(
352 "GIC address {:#x} {:#x} in interrupt-map is different from expected address \
353 {:#x} {:#x}",
354 gic_addr.0, gic_addr.1, 0, 0
355 );
356 return Err(RebootReason::InvalidFdt);
357 }
358
359 if gic_peripheral_interrupt_type != GIC_SPI {
360 error!("GIC peripheral interrupt type {:#x} in interrupt-map is different from expected value \
361 {:#x}", gic_peripheral_interrupt_type, GIC_SPI);
362 return Err(RebootReason::InvalidFdt);
363 }
364
365 let irq_nr: u32 = AARCH64_IRQ_BASE + (idx as u32);
366 if gic_irq_number != irq_nr {
367 error!(
368 "GIC irq number {:#x} in interrupt-map is unexpected. Expected {:#x}",
369 gic_irq_number, irq_nr
370 );
371 return Err(RebootReason::InvalidFdt);
372 }
373
374 if gic_irq_type != IRQ_TYPE_LEVEL_HIGH {
375 error!(
376 "IRQ type in {:#x} is invalid. Must be LEVEL_HIGH {:#x}",
377 gic_irq_type, IRQ_TYPE_LEVEL_HIGH
378 );
379 return Err(RebootReason::InvalidFdt);
Jiyong Park00ceff32023-03-13 05:43:23 +0000380 }
381 Ok(())
382}
383
Jiyong Park9c63cd12023-03-21 17:53:07 +0900384fn patch_pci_info(fdt: &mut Fdt, pci_info: &PciInfo) -> libfdt::Result<()> {
385 let mut node = fdt
386 .root_mut()?
387 .next_compatible(cstr!("pci-host-cam-generic"))?
388 .ok_or(FdtError::NotFound)?;
389
390 let irq_masks_size = pci_info.irq_masks.len() * size_of::<PciIrqMask>();
391 node.trimprop(cstr!("interrupt-map-mask"), irq_masks_size)?;
392
393 let irq_maps_size = pci_info.irq_maps.len() * size_of::<PciIrqMap>();
394 node.trimprop(cstr!("interrupt-map"), irq_maps_size)?;
395
396 node.setprop_inplace(
397 cstr!("ranges"),
398 flatten(&[pci_info.ranges[0].to_cells(), pci_info.ranges[1].to_cells()]),
399 )
400}
401
Jiyong Park00ceff32023-03-13 05:43:23 +0000402#[derive(Default, Debug)]
Jiyong Park6a8789a2023-03-21 14:50:59 +0900403struct SerialInfo {
404 addrs: ArrayVec<[u64; Self::MAX_SERIALS]>,
Jiyong Park00ceff32023-03-13 05:43:23 +0000405}
406
407impl SerialInfo {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900408 const MAX_SERIALS: usize = 4;
Jiyong Park00ceff32023-03-13 05:43:23 +0000409}
410
Jiyong Park6a8789a2023-03-21 14:50:59 +0900411fn read_serial_info_from(fdt: &Fdt) -> libfdt::Result<SerialInfo> {
412 let mut addrs: ArrayVec<[u64; SerialInfo::MAX_SERIALS]> = Default::default();
413 for node in fdt.compatible_nodes(cstr!("ns16550a"))?.take(SerialInfo::MAX_SERIALS) {
414 let reg = node.reg()?.ok_or(FdtError::NotFound)?.next().ok_or(FdtError::NotFound)?;
415 addrs.push(reg.addr);
Jiyong Park00ceff32023-03-13 05:43:23 +0000416 }
Jiyong Park6a8789a2023-03-21 14:50:59 +0900417 Ok(SerialInfo { addrs })
Jiyong Park00ceff32023-03-13 05:43:23 +0000418}
419
Jiyong Park9c63cd12023-03-21 17:53:07 +0900420/// Patch the DT by deleting the ns16550a compatible nodes whose address are unknown
421fn patch_serial_info(fdt: &mut Fdt, serial_info: &SerialInfo) -> libfdt::Result<()> {
422 let name = cstr!("ns16550a");
423 let mut next = fdt.root_mut()?.next_compatible(name);
424 while let Some(current) = next? {
425 let reg = FdtNode::from_mut(&current)
426 .reg()?
427 .ok_or(FdtError::NotFound)?
428 .next()
429 .ok_or(FdtError::NotFound)?;
430 next = if !serial_info.addrs.contains(&reg.addr) {
431 current.delete_and_next_compatible(name)
432 } else {
433 current.next_compatible(name)
434 }
435 }
436 Ok(())
437}
438
Jiyong Park00ceff32023-03-13 05:43:23 +0000439#[derive(Debug)]
Srivatsa Vaddagiri37713ec2023-04-20 04:04:08 -0700440pub struct SwiotlbInfo {
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700441 addr: Option<usize>,
442 size: usize,
Pierre-Clément Tosibe3a97b2023-05-19 14:56:23 +0000443 align: Option<usize>,
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700444}
445
446impl SwiotlbInfo {
447 pub fn fixed_range(&self) -> Option<Range<usize>> {
448 self.addr.map(|addr| addr..addr + self.size)
449 }
Jiyong Park00ceff32023-03-13 05:43:23 +0000450}
451
Jiyong Park6a8789a2023-03-21 14:50:59 +0900452fn read_swiotlb_info_from(fdt: &Fdt) -> libfdt::Result<SwiotlbInfo> {
453 let node =
454 fdt.compatible_nodes(cstr!("restricted-dma-pool"))?.next().ok_or(FdtError::NotFound)?;
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700455
Pierre-Clément Tosibe3a97b2023-05-19 14:56:23 +0000456 let (addr, size, align) = if let Some(mut reg) = node.reg()? {
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700457 let reg = reg.next().ok_or(FdtError::NotFound)?;
458 let size = reg.size.ok_or(FdtError::NotFound)?;
459 reg.addr.checked_add(size).ok_or(FdtError::BadValue)?;
Pierre-Clément Tosibe3a97b2023-05-19 14:56:23 +0000460 (Some(reg.addr.try_into().unwrap()), size.try_into().unwrap(), None)
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700461 } else {
Pierre-Clément Tosibe3a97b2023-05-19 14:56:23 +0000462 let size = node.getprop_u64(cstr!("size"))?.ok_or(FdtError::NotFound)?;
463 let align = node.getprop_u64(cstr!("alignment"))?.ok_or(FdtError::NotFound)?;
464 (None, size.try_into().unwrap(), Some(align.try_into().unwrap()))
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700465 };
466
467 Ok(SwiotlbInfo { addr, size, align })
Jiyong Park6a8789a2023-03-21 14:50:59 +0900468}
Jiyong Park00ceff32023-03-13 05:43:23 +0000469
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700470fn validate_swiotlb_info(
471 swiotlb_info: &SwiotlbInfo,
472 memory: &Range<usize>,
473) -> Result<(), RebootReason> {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900474 let size = swiotlb_info.size;
475 let align = swiotlb_info.align;
Jiyong Park00ceff32023-03-13 05:43:23 +0000476
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700477 if size == 0 || (size % GUEST_PAGE_SIZE) != 0 {
Jiyong Park00ceff32023-03-13 05:43:23 +0000478 error!("Invalid swiotlb size {:#x}", size);
479 return Err(RebootReason::InvalidFdt);
480 }
481
Pierre-Clément Tosibe3a97b2023-05-19 14:56:23 +0000482 if let Some(align) = align.filter(|&a| a % GUEST_PAGE_SIZE != 0) {
Jiyong Park00ceff32023-03-13 05:43:23 +0000483 error!("Invalid swiotlb alignment {:#x}", align);
484 return Err(RebootReason::InvalidFdt);
485 }
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700486
487 if let Some(range) = swiotlb_info.fixed_range() {
488 if !range.is_within(memory) {
489 error!("swiotlb range {range:#x?} not part of memory range {memory:#x?}");
490 return Err(RebootReason::InvalidFdt);
491 }
492 }
493
Jiyong Park6a8789a2023-03-21 14:50:59 +0900494 Ok(())
Jiyong Park00ceff32023-03-13 05:43:23 +0000495}
496
Jiyong Park9c63cd12023-03-21 17:53:07 +0900497fn patch_swiotlb_info(fdt: &mut Fdt, swiotlb_info: &SwiotlbInfo) -> libfdt::Result<()> {
498 let mut node =
499 fdt.root_mut()?.next_compatible(cstr!("restricted-dma-pool"))?.ok_or(FdtError::NotFound)?;
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700500
501 if let Some(range) = swiotlb_info.fixed_range() {
Pierre-Clément Tosic27c4272023-05-19 15:46:26 +0000502 node.setprop_addrrange_inplace(
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700503 cstr!("reg"),
504 range.start.try_into().unwrap(),
505 range.len().try_into().unwrap(),
506 )?;
Pierre-Clément Tosibe3a97b2023-05-19 14:56:23 +0000507 node.nop_property(cstr!("size"))?;
508 node.nop_property(cstr!("alignment"))?;
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700509 } else {
Pierre-Clément Tosic27c4272023-05-19 15:46:26 +0000510 node.nop_property(cstr!("reg"))?;
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700511 node.setprop_inplace(cstr!("size"), &swiotlb_info.size.to_be_bytes())?;
Pierre-Clément Tosibe3a97b2023-05-19 14:56:23 +0000512 node.setprop_inplace(cstr!("alignment"), &swiotlb_info.align.unwrap().to_be_bytes())?;
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700513 }
514
Jiyong Park9c63cd12023-03-21 17:53:07 +0900515 Ok(())
516}
517
518fn patch_gic(fdt: &mut Fdt, num_cpus: usize) -> libfdt::Result<()> {
519 let node = fdt.compatible_nodes(cstr!("arm,gic-v3"))?.next().ok_or(FdtError::NotFound)?;
520 let mut ranges = node.reg()?.ok_or(FdtError::NotFound)?;
521 let range0 = ranges.next().ok_or(FdtError::NotFound)?;
522 let mut range1 = ranges.next().ok_or(FdtError::NotFound)?;
523
524 let addr = range0.addr;
525 // SAFETY - doesn't overflow. checked in validate_num_cpus
526 let size: u64 =
527 DeviceTreeInfo::GIC_REDIST_SIZE_PER_CPU.checked_mul(num_cpus.try_into().unwrap()).unwrap();
528
529 // range1 is just below range0
530 range1.addr = addr - size;
531 range1.size = Some(size);
532
533 let range0 = range0.to_cells();
534 let range1 = range1.to_cells();
535 let value = [
536 range0.0, // addr
537 range0.1.unwrap(), //size
538 range1.0, // addr
539 range1.1.unwrap(), //size
540 ];
541
542 let mut node =
543 fdt.root_mut()?.next_compatible(cstr!("arm,gic-v3"))?.ok_or(FdtError::NotFound)?;
544 node.setprop_inplace(cstr!("reg"), flatten(&value))
545}
546
547fn patch_timer(fdt: &mut Fdt, num_cpus: usize) -> libfdt::Result<()> {
548 const NUM_INTERRUPTS: usize = 4;
549 const CELLS_PER_INTERRUPT: usize = 3;
550 let node = fdt.compatible_nodes(cstr!("arm,armv8-timer"))?.next().ok_or(FdtError::NotFound)?;
551 let interrupts = node.getprop_cells(cstr!("interrupts"))?.ok_or(FdtError::NotFound)?;
552 let mut value: ArrayVec<[u32; NUM_INTERRUPTS * CELLS_PER_INTERRUPT]> =
553 interrupts.take(NUM_INTERRUPTS * CELLS_PER_INTERRUPT).collect();
554
555 let num_cpus: u32 = num_cpus.try_into().unwrap();
556 let cpu_mask: u32 = (((0x1 << num_cpus) - 1) & 0xff) << 8;
557 for v in value.iter_mut().skip(2).step_by(CELLS_PER_INTERRUPT) {
558 *v |= cpu_mask;
559 }
560 for v in value.iter_mut() {
561 *v = v.to_be();
562 }
563
564 // SAFETY - array size is the same
565 let value = unsafe {
566 core::mem::transmute::<
567 [u32; NUM_INTERRUPTS * CELLS_PER_INTERRUPT],
568 [u8; NUM_INTERRUPTS * CELLS_PER_INTERRUPT * size_of::<u32>()],
569 >(value.into_inner())
570 };
571
572 let mut node =
573 fdt.root_mut()?.next_compatible(cstr!("arm,armv8-timer"))?.ok_or(FdtError::NotFound)?;
574 node.setprop_inplace(cstr!("interrupts"), value.as_slice())
575}
576
Jiyong Park00ceff32023-03-13 05:43:23 +0000577#[derive(Debug)]
Jiyong Park6a8789a2023-03-21 14:50:59 +0900578pub struct DeviceTreeInfo {
579 pub kernel_range: Option<Range<usize>>,
580 pub initrd_range: Option<Range<usize>>,
581 pub memory_range: Range<usize>,
Jiyong Parke9d87e82023-03-21 19:28:40 +0900582 bootargs: Option<CString>,
Jiyong Park6a8789a2023-03-21 14:50:59 +0900583 num_cpus: usize,
Jiyong Park00ceff32023-03-13 05:43:23 +0000584 pci_info: PciInfo,
585 serial_info: SerialInfo,
Srivatsa Vaddagiri37713ec2023-04-20 04:04:08 -0700586 pub swiotlb_info: SwiotlbInfo,
Jiyong Park00ceff32023-03-13 05:43:23 +0000587}
588
589impl DeviceTreeInfo {
Jiyong Park9c63cd12023-03-21 17:53:07 +0900590 const GIC_REDIST_SIZE_PER_CPU: u64 = (32 * SIZE_4KB) as u64;
Jiyong Park00ceff32023-03-13 05:43:23 +0000591}
592
Jiyong Park9c63cd12023-03-21 17:53:07 +0900593pub fn sanitize_device_tree(fdt: &mut Fdt) -> Result<DeviceTreeInfo, RebootReason> {
Jiyong Park83316122023-03-21 09:39:39 +0900594 let info = parse_device_tree(fdt)?;
595 debug!("Device tree info: {:?}", info);
596
Jiyong Parke9d87e82023-03-21 19:28:40 +0900597 fdt.copy_from_slice(pvmfw_fdt_template::RAW).map_err(|e| {
598 error!("Failed to instantiate FDT from the template DT: {e}");
599 RebootReason::InvalidFdt
600 })?;
601
Jiyong Park9c63cd12023-03-21 17:53:07 +0900602 patch_device_tree(fdt, &info)?;
Jiyong Park6a8789a2023-03-21 14:50:59 +0900603 Ok(info)
Jiyong Park83316122023-03-21 09:39:39 +0900604}
605
606fn parse_device_tree(fdt: &libfdt::Fdt) -> Result<DeviceTreeInfo, RebootReason> {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900607 let kernel_range = read_kernel_range_from(fdt).map_err(|e| {
608 error!("Failed to read kernel range from DT: {e}");
609 RebootReason::InvalidFdt
610 })?;
611
612 let initrd_range = read_initrd_range_from(fdt).map_err(|e| {
613 error!("Failed to read initrd range from DT: {e}");
614 RebootReason::InvalidFdt
615 })?;
616
617 let memory_range = read_memory_range_from(fdt).map_err(|e| {
618 error!("Failed to read memory range from DT: {e}");
619 RebootReason::InvalidFdt
620 })?;
621 validate_memory_range(&memory_range)?;
622
Jiyong Parke9d87e82023-03-21 19:28:40 +0900623 let bootargs = read_bootargs_from(fdt).map_err(|e| {
624 error!("Failed to read bootargs from DT: {e}");
625 RebootReason::InvalidFdt
626 })?;
627
Jiyong Park6a8789a2023-03-21 14:50:59 +0900628 let num_cpus = read_num_cpus_from(fdt).map_err(|e| {
629 error!("Failed to read num cpus from DT: {e}");
630 RebootReason::InvalidFdt
631 })?;
632 validate_num_cpus(num_cpus)?;
633
634 let pci_info = read_pci_info_from(fdt).map_err(|e| {
635 error!("Failed to read pci info from DT: {e}");
636 RebootReason::InvalidFdt
637 })?;
Jiyong Park0ee65392023-03-27 20:52:45 +0900638 validate_pci_info(&pci_info, &memory_range)?;
Jiyong Park6a8789a2023-03-21 14:50:59 +0900639
640 let serial_info = read_serial_info_from(fdt).map_err(|e| {
641 error!("Failed to read serial info from DT: {e}");
642 RebootReason::InvalidFdt
643 })?;
644
645 let swiotlb_info = read_swiotlb_info_from(fdt).map_err(|e| {
646 error!("Failed to read swiotlb info from DT: {e}");
647 RebootReason::InvalidFdt
648 })?;
Srivatsa Vaddagiri2df297f2023-04-12 03:11:05 -0700649 validate_swiotlb_info(&swiotlb_info, &memory_range)?;
Jiyong Park6a8789a2023-03-21 14:50:59 +0900650
Jiyong Park00ceff32023-03-13 05:43:23 +0000651 Ok(DeviceTreeInfo {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900652 kernel_range,
653 initrd_range,
654 memory_range,
Jiyong Parke9d87e82023-03-21 19:28:40 +0900655 bootargs,
Jiyong Park6a8789a2023-03-21 14:50:59 +0900656 num_cpus,
657 pci_info,
658 serial_info,
659 swiotlb_info,
Jiyong Park00ceff32023-03-13 05:43:23 +0000660 })
661}
662
Jiyong Park9c63cd12023-03-21 17:53:07 +0900663fn patch_device_tree(fdt: &mut Fdt, info: &DeviceTreeInfo) -> Result<(), RebootReason> {
Jiyong Parke9d87e82023-03-21 19:28:40 +0900664 fdt.unpack().map_err(|e| {
665 error!("Failed to unpack DT for patching: {e}");
666 RebootReason::InvalidFdt
667 })?;
668
Jiyong Park9c63cd12023-03-21 17:53:07 +0900669 if let Some(initrd_range) = &info.initrd_range {
670 patch_initrd_range(fdt, initrd_range).map_err(|e| {
671 error!("Failed to patch initrd range to DT: {e}");
672 RebootReason::InvalidFdt
673 })?;
674 }
675 patch_memory_range(fdt, &info.memory_range).map_err(|e| {
676 error!("Failed to patch memory range to DT: {e}");
677 RebootReason::InvalidFdt
678 })?;
Jiyong Parke9d87e82023-03-21 19:28:40 +0900679 if let Some(bootargs) = &info.bootargs {
680 patch_bootargs(fdt, bootargs.as_c_str()).map_err(|e| {
681 error!("Failed to patch bootargs to DT: {e}");
682 RebootReason::InvalidFdt
683 })?;
684 }
Jiyong Park9c63cd12023-03-21 17:53:07 +0900685 patch_num_cpus(fdt, info.num_cpus).map_err(|e| {
686 error!("Failed to patch cpus to DT: {e}");
687 RebootReason::InvalidFdt
688 })?;
689 patch_pci_info(fdt, &info.pci_info).map_err(|e| {
690 error!("Failed to patch pci info to DT: {e}");
691 RebootReason::InvalidFdt
692 })?;
693 patch_serial_info(fdt, &info.serial_info).map_err(|e| {
694 error!("Failed to patch serial info to DT: {e}");
695 RebootReason::InvalidFdt
696 })?;
697 patch_swiotlb_info(fdt, &info.swiotlb_info).map_err(|e| {
698 error!("Failed to patch swiotlb info to DT: {e}");
699 RebootReason::InvalidFdt
700 })?;
701 patch_gic(fdt, info.num_cpus).map_err(|e| {
702 error!("Failed to patch gic info to DT: {e}");
703 RebootReason::InvalidFdt
704 })?;
705 patch_timer(fdt, info.num_cpus).map_err(|e| {
706 error!("Failed to patch timer info to DT: {e}");
707 RebootReason::InvalidFdt
708 })?;
Jiyong Parke9d87e82023-03-21 19:28:40 +0900709
710 fdt.pack().map_err(|e| {
711 error!("Failed to pack DT after patching: {e}");
712 RebootReason::InvalidFdt
713 })?;
714
Jiyong Park9c63cd12023-03-21 17:53:07 +0900715 Ok(())
716}
717
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000718/// Modifies the input DT according to the fields of the configuration.
719pub fn modify_for_next_stage(
720 fdt: &mut Fdt,
721 bcc: &[u8],
722 new_instance: bool,
723 strict_boot: bool,
Jiyong Parkc23426b2023-04-10 17:32:27 +0900724 debug_policy: Option<&mut [u8]>,
Jiyong Parkc5d2ef22023-04-11 01:23:46 +0900725 debuggable: bool,
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000726) -> libfdt::Result<()> {
Pierre-Clément Tosieb887ac2023-05-02 13:33:37 +0000727 if let Some(debug_policy) = debug_policy {
728 let backup = Vec::from(fdt.as_slice());
729 fdt.unpack()?;
730 let backup_fdt = Fdt::from_slice(backup.as_slice()).unwrap();
731 if apply_debug_policy(fdt, backup_fdt, debug_policy)? {
732 info!("Debug policy applied.");
733 } else {
734 // apply_debug_policy restored fdt to backup_fdt so unpack it again.
735 fdt.unpack()?;
736 }
737 } else {
738 info!("No debug policy found.");
739 fdt.unpack()?;
740 }
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000741
Jiyong Parke9d87e82023-03-21 19:28:40 +0900742 patch_dice_node(fdt, bcc.as_ptr() as usize, bcc.len())?;
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000743
Jiyong Parkb87f3302023-03-21 10:03:11 +0900744 set_or_clear_chosen_flag(fdt, cstr!("avf,strict-boot"), strict_boot)?;
745 set_or_clear_chosen_flag(fdt, cstr!("avf,new-instance"), new_instance)?;
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000746
Jiyong Park32f37ef2023-05-17 16:15:58 +0900747 if !debuggable {
Jiyong Parkc5d2ef22023-04-11 01:23:46 +0900748 if let Some(bootargs) = read_bootargs_from(fdt)? {
749 filter_out_dangerous_bootargs(fdt, &bootargs)?;
750 }
751 }
752
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000753 fdt.pack()?;
754
755 Ok(())
756}
757
Jiyong Parke9d87e82023-03-21 19:28:40 +0900758/// Patch the "google,open-dice"-compatible reserved-memory node to point to the bcc range
759fn patch_dice_node(fdt: &mut Fdt, addr: usize, size: usize) -> libfdt::Result<()> {
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000760 // We reject DTs with missing reserved-memory node as validation should have checked that the
761 // "swiotlb" subnode (compatible = "restricted-dma-pool") was present.
Jiyong Parke9d87e82023-03-21 19:28:40 +0900762 let node = fdt.node_mut(cstr!("/reserved-memory"))?.ok_or(libfdt::FdtError::NotFound)?;
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000763
Jiyong Parke9d87e82023-03-21 19:28:40 +0900764 let mut node = node.next_compatible(cstr!("google,open-dice"))?.ok_or(FdtError::NotFound)?;
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000765
Jiyong Parke9d87e82023-03-21 19:28:40 +0900766 let addr: u64 = addr.try_into().unwrap();
767 let size: u64 = size.try_into().unwrap();
768 node.setprop_inplace(cstr!("reg"), flatten(&[addr.to_be_bytes(), size.to_be_bytes()]))
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000769}
770
771fn set_or_clear_chosen_flag(fdt: &mut Fdt, flag: &CStr, value: bool) -> libfdt::Result<()> {
772 // TODO(b/249054080): Refactor to not panic if the DT doesn't contain a /chosen node.
773 let mut chosen = fdt.chosen_mut()?.unwrap();
774 if value {
775 chosen.setprop_empty(flag)?;
776 } else {
777 match chosen.delprop(flag) {
778 Ok(()) | Err(FdtError::NotFound) => (),
779 Err(e) => return Err(e),
780 }
781 }
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000782
783 Ok(())
784}
Jiyong Parkc23426b2023-04-10 17:32:27 +0900785
Pierre-Clément Tosia50167b2023-05-02 13:19:29 +0000786/// Apply the debug policy overlay to the guest DT.
787///
788/// Returns Ok(true) on success, Ok(false) on recovered failure and Err(_) on corruption of the DT.
Pierre-Clément Tosieb887ac2023-05-02 13:33:37 +0000789fn apply_debug_policy(
790 fdt: &mut Fdt,
791 backup_fdt: &Fdt,
792 debug_policy: &[u8],
793) -> libfdt::Result<bool> {
Pierre-Clément Tosia50167b2023-05-02 13:19:29 +0000794 let mut debug_policy = Vec::from(debug_policy);
795 let overlay = match Fdt::from_mut_slice(debug_policy.as_mut_slice()) {
Jiyong Parkc23426b2023-04-10 17:32:27 +0900796 Ok(overlay) => overlay,
797 Err(e) => {
Pierre-Clément Tosia50167b2023-05-02 13:19:29 +0000798 warn!("Corrupted debug policy found: {e}. Not applying.");
799 return Ok(false);
Jiyong Parkc23426b2023-04-10 17:32:27 +0900800 }
801 };
Jiyong Parkc23426b2023-04-10 17:32:27 +0900802
Pierre-Clément Tosia50167b2023-05-02 13:19:29 +0000803 // SAFETY - on failure, the corrupted DT is restored using the backup.
Jiyong Parkc23426b2023-04-10 17:32:27 +0900804 if let Err(e) = unsafe { fdt.apply_overlay(overlay) } {
Pierre-Clément Tosia50167b2023-05-02 13:19:29 +0000805 warn!("Failed to apply debug policy: {e}. Recovering...");
Jiyong Parkc23426b2023-04-10 17:32:27 +0900806 fdt.copy_from_slice(backup_fdt.as_slice())?;
Jiyong Parkc23426b2023-04-10 17:32:27 +0900807 // A successful restoration is considered success because an invalid debug policy
808 // shouldn't DOS the pvmfw
Pierre-Clément Tosia50167b2023-05-02 13:19:29 +0000809 Ok(false)
810 } else {
811 Ok(true)
Jiyong Parkc23426b2023-04-10 17:32:27 +0900812 }
Jiyong Parkc23426b2023-04-10 17:32:27 +0900813}
Jiyong Parkc5d2ef22023-04-11 01:23:46 +0900814
815fn read_common_debug_policy(fdt: &Fdt, debug_feature_name: &CStr) -> libfdt::Result<bool> {
816 if let Some(node) = fdt.node(cstr!("/avf/guest/common"))? {
817 if let Some(value) = node.getprop_u32(debug_feature_name)? {
818 return Ok(value == 1);
819 }
820 }
821 Ok(false) // if the policy doesn't exist or not 1, don't enable the debug feature
822}
823
824fn filter_out_dangerous_bootargs(fdt: &mut Fdt, bootargs: &CStr) -> libfdt::Result<()> {
825 let has_crashkernel = read_common_debug_policy(fdt, cstr!("ramdump"))?;
826 let has_console = read_common_debug_policy(fdt, cstr!("log"))?;
827
828 let accepted: &[(&str, Box<dyn Fn(Option<&str>) -> bool>)] = &[
829 ("panic", Box::new(|v| if let Some(v) = v { v == "=-1" } else { false })),
830 ("crashkernel", Box::new(|_| has_crashkernel)),
831 ("console", Box::new(|_| has_console)),
832 ];
833
834 // parse and filter out unwanted
835 let mut filtered = Vec::new();
836 for arg in BootArgsIterator::new(bootargs).map_err(|e| {
837 info!("Invalid bootarg: {e}");
838 FdtError::BadValue
839 })? {
840 match accepted.iter().find(|&t| t.0 == arg.name()) {
841 Some((_, pred)) if pred(arg.value()) => filtered.push(arg),
842 _ => debug!("Rejected bootarg {}", arg.as_ref()),
843 }
844 }
845
846 // flatten into a new C-string
847 let mut new_bootargs = Vec::new();
848 for (i, arg) in filtered.iter().enumerate() {
849 if i != 0 {
850 new_bootargs.push(b' '); // separator
851 }
852 new_bootargs.extend_from_slice(arg.as_ref().as_bytes());
853 }
854 new_bootargs.push(b'\0');
855
856 let mut node = fdt.chosen_mut()?.ok_or(FdtError::NotFound)?;
857 node.setprop(cstr!("bootargs"), new_bootargs.as_slice())
858}