blob: 7d8845573336c7d6f37c9218b26e9cbfa3dea032 [file] [log] [blame]
Pierre-Clément Tosia0934c12022-11-25 20:54:11 +00001// Copyright 2022, The Android Open Source Project
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15//! High-level FDT functions.
16
Jiyong Parkb87f3302023-03-21 10:03:11 +090017use crate::cstr;
Jiyong Park9c63cd12023-03-21 17:53:07 +090018use crate::helpers::flatten;
Jiyong Park00ceff32023-03-13 05:43:23 +000019use crate::helpers::GUEST_PAGE_SIZE;
Jiyong Park9c63cd12023-03-21 17:53:07 +090020use crate::helpers::SIZE_4KB;
Jiyong Park0ee65392023-03-27 20:52:45 +090021use crate::memory::BASE_ADDR;
22use crate::memory::MAX_ADDR;
Jiyong Park00ceff32023-03-13 05:43:23 +000023use crate::RebootReason;
Jiyong Parke9d87e82023-03-21 19:28:40 +090024use alloc::ffi::CString;
Jiyong Park0ee65392023-03-27 20:52:45 +090025use core::cmp::max;
26use core::cmp::min;
Pierre-Clément Tosia0934c12022-11-25 20:54:11 +000027use core::ffi::CStr;
Jiyong Park9c63cd12023-03-21 17:53:07 +090028use core::mem::size_of;
Pierre-Clément Tosia0934c12022-11-25 20:54:11 +000029use core::ops::Range;
Jiyong Park00ceff32023-03-13 05:43:23 +000030use fdtpci::PciMemoryFlags;
31use fdtpci::PciRangeType;
32use libfdt::AddressRange;
33use libfdt::CellIterator;
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +000034use libfdt::Fdt;
35use libfdt::FdtError;
Jiyong Park9c63cd12023-03-21 17:53:07 +090036use libfdt::FdtNode;
Jiyong Park83316122023-03-21 09:39:39 +090037use log::debug;
Jiyong Park00ceff32023-03-13 05:43:23 +000038use log::error;
39use tinyvec::ArrayVec;
Pierre-Clément Tosia0934c12022-11-25 20:54:11 +000040
Jiyong Park6a8789a2023-03-21 14:50:59 +090041/// Extract from /config the address range containing the pre-loaded kernel. Absence of /config is
42/// not an error.
43fn read_kernel_range_from(fdt: &Fdt) -> libfdt::Result<Option<Range<usize>>> {
Jiyong Parkb87f3302023-03-21 10:03:11 +090044 let addr = cstr!("kernel-address");
45 let size = cstr!("kernel-size");
Pierre-Clément Tosic3811b82022-11-29 11:24:16 +000046
Jiyong Parkb87f3302023-03-21 10:03:11 +090047 if let Some(config) = fdt.node(cstr!("/config"))? {
Pierre-Clément Tosic3811b82022-11-29 11:24:16 +000048 if let (Some(addr), Some(size)) = (config.getprop_u32(addr)?, config.getprop_u32(size)?) {
49 let addr = addr as usize;
50 let size = size as usize;
51
52 return Ok(Some(addr..(addr + size)));
53 }
54 }
55
56 Ok(None)
57}
58
Jiyong Park6a8789a2023-03-21 14:50:59 +090059/// Extract from /chosen the address range containing the pre-loaded ramdisk. Absence is not an
60/// error as there can be initrd-less VM.
61fn read_initrd_range_from(fdt: &Fdt) -> libfdt::Result<Option<Range<usize>>> {
Jiyong Parkb87f3302023-03-21 10:03:11 +090062 let start = cstr!("linux,initrd-start");
63 let end = cstr!("linux,initrd-end");
Pierre-Clément Tosia0934c12022-11-25 20:54:11 +000064
65 if let Some(chosen) = fdt.chosen()? {
66 if let (Some(start), Some(end)) = (chosen.getprop_u32(start)?, chosen.getprop_u32(end)?) {
67 return Ok(Some((start as usize)..(end as usize)));
68 }
69 }
70
71 Ok(None)
72}
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +000073
Jiyong Park9c63cd12023-03-21 17:53:07 +090074fn patch_initrd_range(fdt: &mut Fdt, initrd_range: &Range<usize>) -> libfdt::Result<()> {
75 let start = u32::try_from(initrd_range.start).unwrap();
76 let end = u32::try_from(initrd_range.end).unwrap();
77
78 let mut node = fdt.chosen_mut()?.ok_or(FdtError::NotFound)?;
79 node.setprop(cstr!("linux,initrd-start"), &start.to_be_bytes())?;
80 node.setprop(cstr!("linux,initrd-end"), &end.to_be_bytes())?;
81 Ok(())
82}
83
Jiyong Parke9d87e82023-03-21 19:28:40 +090084fn read_bootargs_from(fdt: &Fdt) -> libfdt::Result<Option<CString>> {
85 if let Some(chosen) = fdt.chosen()? {
86 if let Some(bootargs) = chosen.getprop_str(cstr!("bootargs"))? {
87 // We need to copy the string to heap because the original fdt will be invalidated
88 // by the templated DT
89 let copy = CString::new(bootargs.to_bytes()).map_err(|_| FdtError::BadValue)?;
90 return Ok(Some(copy));
91 }
92 }
93 Ok(None)
94}
95
96fn patch_bootargs(fdt: &mut Fdt, bootargs: &CStr) -> libfdt::Result<()> {
97 let mut node = fdt.chosen_mut()?.ok_or(FdtError::NotFound)?;
98 // TODO(b/275306568) filter out dangerous options
99 node.setprop(cstr!("bootargs"), bootargs.to_bytes_with_nul())
100}
101
Jiyong Park6a8789a2023-03-21 14:50:59 +0900102/// Read the first range in /memory node in DT
103fn read_memory_range_from(fdt: &Fdt) -> libfdt::Result<Range<usize>> {
104 fdt.memory()?.ok_or(FdtError::NotFound)?.next().ok_or(FdtError::NotFound)
105}
Jiyong Park00ceff32023-03-13 05:43:23 +0000106
Jiyong Park6a8789a2023-03-21 14:50:59 +0900107/// Check if memory range is ok
108fn validate_memory_range(range: &Range<usize>) -> Result<(), RebootReason> {
109 let base = range.start;
Jiyong Park0ee65392023-03-27 20:52:45 +0900110 if base != BASE_ADDR {
111 error!("Memory base address {:#x} is not {:#x}", base, BASE_ADDR);
Jiyong Park00ceff32023-03-13 05:43:23 +0000112 return Err(RebootReason::InvalidFdt);
113 }
114
Jiyong Park6a8789a2023-03-21 14:50:59 +0900115 let size = range.len();
Jiyong Park00ceff32023-03-13 05:43:23 +0000116 if size % GUEST_PAGE_SIZE != 0 {
117 error!("Memory size {:#x} is not a multiple of page size {:#x}", size, GUEST_PAGE_SIZE);
118 return Err(RebootReason::InvalidFdt);
119 }
Jiyong Park00ceff32023-03-13 05:43:23 +0000120
Jiyong Park6a8789a2023-03-21 14:50:59 +0900121 if size == 0 {
122 error!("Memory size is 0");
123 return Err(RebootReason::InvalidFdt);
124 }
125 Ok(())
Jiyong Park00ceff32023-03-13 05:43:23 +0000126}
127
Jiyong Park9c63cd12023-03-21 17:53:07 +0900128fn patch_memory_range(fdt: &mut Fdt, memory_range: &Range<usize>) -> libfdt::Result<()> {
129 let size = memory_range.len() as u64;
Jiyong Park0ee65392023-03-27 20:52:45 +0900130 fdt.node_mut(cstr!("/memory"))?
131 .ok_or(FdtError::NotFound)?
132 .setprop_inplace(cstr!("reg"), flatten(&[BASE_ADDR.to_be_bytes(), size.to_be_bytes()]))
Jiyong Park9c63cd12023-03-21 17:53:07 +0900133}
134
Jiyong Park6a8789a2023-03-21 14:50:59 +0900135/// Read the number of CPUs from DT
136fn read_num_cpus_from(fdt: &Fdt) -> libfdt::Result<usize> {
137 Ok(fdt.compatible_nodes(cstr!("arm,arm-v8"))?.count())
138}
139
140/// Validate number of CPUs
141fn validate_num_cpus(num_cpus: usize) -> Result<(), RebootReason> {
142 if num_cpus == 0 {
Jiyong Park00ceff32023-03-13 05:43:23 +0000143 error!("Number of CPU can't be 0");
Jiyong Park6a8789a2023-03-21 14:50:59 +0900144 return Err(RebootReason::InvalidFdt);
145 }
Jiyong Park9c63cd12023-03-21 17:53:07 +0900146 if DeviceTreeInfo::GIC_REDIST_SIZE_PER_CPU.checked_mul(num_cpus.try_into().unwrap()).is_none() {
147 error!("Too many CPUs for gic: {}", num_cpus);
148 return Err(RebootReason::InvalidFdt);
149 }
150 Ok(())
151}
152
153/// Patch DT by keeping `num_cpus` number of arm,arm-v8 compatible nodes, and pruning the rest.
154fn patch_num_cpus(fdt: &mut Fdt, num_cpus: usize) -> libfdt::Result<()> {
155 let cpu = cstr!("arm,arm-v8");
156 let mut next = fdt.root_mut()?.next_compatible(cpu)?;
157 for _ in 0..num_cpus {
158 next = if let Some(current) = next {
159 current.next_compatible(cpu)?
160 } else {
161 return Err(FdtError::NoSpace);
162 };
163 }
164 while let Some(current) = next {
165 next = current.delete_and_next_compatible(cpu)?;
166 }
Jiyong Park6a8789a2023-03-21 14:50:59 +0900167 Ok(())
Jiyong Park00ceff32023-03-13 05:43:23 +0000168}
169
170#[derive(Debug)]
Jiyong Park00ceff32023-03-13 05:43:23 +0000171struct PciInfo {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900172 ranges: [PciAddrRange; 2],
173 irq_masks: ArrayVec<[PciIrqMask; PciInfo::MAX_IRQS]>,
174 irq_maps: ArrayVec<[PciIrqMap; PciInfo::MAX_IRQS]>,
Jiyong Park00ceff32023-03-13 05:43:23 +0000175}
176
Jiyong Park6a8789a2023-03-21 14:50:59 +0900177impl PciInfo {
178 const IRQ_MASK_CELLS: usize = 4;
179 const IRQ_MAP_CELLS: usize = 10;
180 const MAX_IRQS: usize = 8;
Jiyong Park00ceff32023-03-13 05:43:23 +0000181}
182
Jiyong Park6a8789a2023-03-21 14:50:59 +0900183type PciAddrRange = AddressRange<(u32, u64), u64, u64>;
184type PciIrqMask = [u32; PciInfo::IRQ_MASK_CELLS];
185type PciIrqMap = [u32; PciInfo::IRQ_MAP_CELLS];
Jiyong Park00ceff32023-03-13 05:43:23 +0000186
187/// Iterator that takes N cells as a chunk
188struct CellChunkIterator<'a, const N: usize> {
189 cells: CellIterator<'a>,
190}
191
192impl<'a, const N: usize> CellChunkIterator<'a, N> {
193 fn new(cells: CellIterator<'a>) -> Self {
194 Self { cells }
195 }
196}
197
198impl<'a, const N: usize> Iterator for CellChunkIterator<'a, N> {
199 type Item = [u32; N];
200 fn next(&mut self) -> Option<Self::Item> {
201 let mut ret: Self::Item = [0; N];
202 for i in ret.iter_mut() {
203 *i = self.cells.next()?;
204 }
205 Some(ret)
206 }
207}
208
Jiyong Park6a8789a2023-03-21 14:50:59 +0900209/// Read pci host controller ranges, irq maps, and irq map masks from DT
210fn read_pci_info_from(fdt: &Fdt) -> libfdt::Result<PciInfo> {
211 let node =
212 fdt.compatible_nodes(cstr!("pci-host-cam-generic"))?.next().ok_or(FdtError::NotFound)?;
213
214 let mut ranges = node.ranges::<(u32, u64), u64, u64>()?.ok_or(FdtError::NotFound)?;
215 let range0 = ranges.next().ok_or(FdtError::NotFound)?;
216 let range1 = ranges.next().ok_or(FdtError::NotFound)?;
217
218 let irq_masks = node.getprop_cells(cstr!("interrupt-map-mask"))?.ok_or(FdtError::NotFound)?;
219 let irq_masks = CellChunkIterator::<{ PciInfo::IRQ_MASK_CELLS }>::new(irq_masks);
220 let irq_masks: ArrayVec<[PciIrqMask; PciInfo::MAX_IRQS]> =
221 irq_masks.take(PciInfo::MAX_IRQS).collect();
222
223 let irq_maps = node.getprop_cells(cstr!("interrupt-map"))?.ok_or(FdtError::NotFound)?;
224 let irq_maps = CellChunkIterator::<{ PciInfo::IRQ_MAP_CELLS }>::new(irq_maps);
225 let irq_maps: ArrayVec<[PciIrqMap; PciInfo::MAX_IRQS]> =
226 irq_maps.take(PciInfo::MAX_IRQS).collect();
227
228 Ok(PciInfo { ranges: [range0, range1], irq_masks, irq_maps })
229}
230
Jiyong Park0ee65392023-03-27 20:52:45 +0900231fn validate_pci_info(pci_info: &PciInfo, memory_range: &Range<usize>) -> Result<(), RebootReason> {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900232 for range in pci_info.ranges.iter() {
Jiyong Park0ee65392023-03-27 20:52:45 +0900233 validate_pci_addr_range(range, memory_range)?;
Jiyong Park6a8789a2023-03-21 14:50:59 +0900234 }
235 for irq_mask in pci_info.irq_masks.iter() {
236 validate_pci_irq_mask(irq_mask)?;
237 }
238 for (idx, irq_map) in pci_info.irq_maps.iter().enumerate() {
239 validate_pci_irq_map(irq_map, idx)?;
240 }
241 Ok(())
242}
243
Jiyong Park0ee65392023-03-27 20:52:45 +0900244fn validate_pci_addr_range(
245 range: &PciAddrRange,
246 memory_range: &Range<usize>,
247) -> Result<(), RebootReason> {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900248 let mem_flags = PciMemoryFlags(range.addr.0);
249 let range_type = mem_flags.range_type();
250 let prefetchable = mem_flags.prefetchable();
251 let bus_addr = range.addr.1;
252 let cpu_addr = range.parent_addr;
253 let size = range.size;
254
255 if range_type != PciRangeType::Memory64 {
256 error!("Invalid range type {:?} for bus address {:#x} in PCI node", range_type, bus_addr);
257 return Err(RebootReason::InvalidFdt);
258 }
259 if prefetchable {
260 error!("PCI bus address {:#x} in PCI node is prefetchable", bus_addr);
261 return Err(RebootReason::InvalidFdt);
262 }
263 // Enforce ID bus-to-cpu mappings, as used by crosvm.
264 if bus_addr != cpu_addr {
265 error!("PCI bus address: {:#x} is different from CPU address: {:#x}", bus_addr, cpu_addr);
266 return Err(RebootReason::InvalidFdt);
267 }
268
Jiyong Park0ee65392023-03-27 20:52:45 +0900269 let Some(bus_end) = bus_addr.checked_add(size) else {
270 error!("PCI address range size {:#x} overflows", size);
271 return Err(RebootReason::InvalidFdt);
272 };
273 if bus_end > MAX_ADDR.try_into().unwrap() {
274 error!("PCI address end {:#x} is outside of translatable range", bus_end);
275 return Err(RebootReason::InvalidFdt);
276 }
277
278 let memory_start = memory_range.start.try_into().unwrap();
279 let memory_end = memory_range.end.try_into().unwrap();
280
281 if max(bus_addr, memory_start) < min(bus_end, memory_end) {
282 error!(
283 "PCI address range {:#x}-{:#x} overlaps with main memory range {:#x}-{:#x}",
284 bus_addr, bus_end, memory_start, memory_end
285 );
Jiyong Park6a8789a2023-03-21 14:50:59 +0900286 return Err(RebootReason::InvalidFdt);
287 }
288
289 Ok(())
290}
291
292fn validate_pci_irq_mask(irq_mask: &PciIrqMask) -> Result<(), RebootReason> {
Jiyong Park00ceff32023-03-13 05:43:23 +0000293 const IRQ_MASK_ADDR_HI: u32 = 0xf800;
294 const IRQ_MASK_ADDR_ME: u32 = 0x0;
295 const IRQ_MASK_ADDR_LO: u32 = 0x0;
296 const IRQ_MASK_ANY_IRQ: u32 = 0x7;
Jiyong Park6a8789a2023-03-21 14:50:59 +0900297 const EXPECTED: PciIrqMask =
Jiyong Park00ceff32023-03-13 05:43:23 +0000298 [IRQ_MASK_ADDR_HI, IRQ_MASK_ADDR_ME, IRQ_MASK_ADDR_LO, IRQ_MASK_ANY_IRQ];
Jiyong Park6a8789a2023-03-21 14:50:59 +0900299 if *irq_mask != EXPECTED {
300 error!("Invalid PCI irq mask {:#?}", irq_mask);
301 return Err(RebootReason::InvalidFdt);
Jiyong Park00ceff32023-03-13 05:43:23 +0000302 }
Jiyong Park6a8789a2023-03-21 14:50:59 +0900303 Ok(())
Jiyong Park00ceff32023-03-13 05:43:23 +0000304}
305
Jiyong Park6a8789a2023-03-21 14:50:59 +0900306fn validate_pci_irq_map(irq_map: &PciIrqMap, idx: usize) -> Result<(), RebootReason> {
Jiyong Park00ceff32023-03-13 05:43:23 +0000307 const PCI_DEVICE_IDX: usize = 11;
308 const PCI_IRQ_ADDR_ME: u32 = 0;
309 const PCI_IRQ_ADDR_LO: u32 = 0;
310 const PCI_IRQ_INTC: u32 = 1;
311 const AARCH64_IRQ_BASE: u32 = 4; // from external/crosvm/aarch64/src/lib.rs
312 const GIC_SPI: u32 = 0;
313 const IRQ_TYPE_LEVEL_HIGH: u32 = 4;
314
Jiyong Park6a8789a2023-03-21 14:50:59 +0900315 let pci_addr = (irq_map[0], irq_map[1], irq_map[2]);
316 let pci_irq_number = irq_map[3];
317 let _controller_phandle = irq_map[4]; // skipped.
318 let gic_addr = (irq_map[5], irq_map[6]); // address-cells is <2> for GIC
319 // interrupt-cells is <3> for GIC
320 let gic_peripheral_interrupt_type = irq_map[7];
321 let gic_irq_number = irq_map[8];
322 let gic_irq_type = irq_map[9];
Jiyong Park00ceff32023-03-13 05:43:23 +0000323
Jiyong Park6a8789a2023-03-21 14:50:59 +0900324 let phys_hi: u32 = (0x1 << PCI_DEVICE_IDX) * (idx + 1) as u32;
325 let expected_pci_addr = (phys_hi, PCI_IRQ_ADDR_ME, PCI_IRQ_ADDR_LO);
Jiyong Park00ceff32023-03-13 05:43:23 +0000326
Jiyong Park6a8789a2023-03-21 14:50:59 +0900327 if pci_addr != expected_pci_addr {
328 error!("PCI device address {:#x} {:#x} {:#x} in interrupt-map is different from expected address \
329 {:#x} {:#x} {:#x}",
330 pci_addr.0, pci_addr.1, pci_addr.2, expected_pci_addr.0, expected_pci_addr.1, expected_pci_addr.2);
331 return Err(RebootReason::InvalidFdt);
332 }
Jiyong Park00ceff32023-03-13 05:43:23 +0000333
Jiyong Park6a8789a2023-03-21 14:50:59 +0900334 if pci_irq_number != PCI_IRQ_INTC {
335 error!(
336 "PCI INT# {:#x} in interrupt-map is different from expected value {:#x}",
337 pci_irq_number, PCI_IRQ_INTC
338 );
339 return Err(RebootReason::InvalidFdt);
340 }
Jiyong Park00ceff32023-03-13 05:43:23 +0000341
Jiyong Park6a8789a2023-03-21 14:50:59 +0900342 if gic_addr != (0, 0) {
343 error!(
344 "GIC address {:#x} {:#x} in interrupt-map is different from expected address \
345 {:#x} {:#x}",
346 gic_addr.0, gic_addr.1, 0, 0
347 );
348 return Err(RebootReason::InvalidFdt);
349 }
350
351 if gic_peripheral_interrupt_type != GIC_SPI {
352 error!("GIC peripheral interrupt type {:#x} in interrupt-map is different from expected value \
353 {:#x}", gic_peripheral_interrupt_type, GIC_SPI);
354 return Err(RebootReason::InvalidFdt);
355 }
356
357 let irq_nr: u32 = AARCH64_IRQ_BASE + (idx as u32);
358 if gic_irq_number != irq_nr {
359 error!(
360 "GIC irq number {:#x} in interrupt-map is unexpected. Expected {:#x}",
361 gic_irq_number, irq_nr
362 );
363 return Err(RebootReason::InvalidFdt);
364 }
365
366 if gic_irq_type != IRQ_TYPE_LEVEL_HIGH {
367 error!(
368 "IRQ type in {:#x} is invalid. Must be LEVEL_HIGH {:#x}",
369 gic_irq_type, IRQ_TYPE_LEVEL_HIGH
370 );
371 return Err(RebootReason::InvalidFdt);
Jiyong Park00ceff32023-03-13 05:43:23 +0000372 }
373 Ok(())
374}
375
Jiyong Park9c63cd12023-03-21 17:53:07 +0900376fn patch_pci_info(fdt: &mut Fdt, pci_info: &PciInfo) -> libfdt::Result<()> {
377 let mut node = fdt
378 .root_mut()?
379 .next_compatible(cstr!("pci-host-cam-generic"))?
380 .ok_or(FdtError::NotFound)?;
381
382 let irq_masks_size = pci_info.irq_masks.len() * size_of::<PciIrqMask>();
383 node.trimprop(cstr!("interrupt-map-mask"), irq_masks_size)?;
384
385 let irq_maps_size = pci_info.irq_maps.len() * size_of::<PciIrqMap>();
386 node.trimprop(cstr!("interrupt-map"), irq_maps_size)?;
387
388 node.setprop_inplace(
389 cstr!("ranges"),
390 flatten(&[pci_info.ranges[0].to_cells(), pci_info.ranges[1].to_cells()]),
391 )
392}
393
Jiyong Park00ceff32023-03-13 05:43:23 +0000394#[derive(Default, Debug)]
Jiyong Park6a8789a2023-03-21 14:50:59 +0900395struct SerialInfo {
396 addrs: ArrayVec<[u64; Self::MAX_SERIALS]>,
Jiyong Park00ceff32023-03-13 05:43:23 +0000397}
398
399impl SerialInfo {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900400 const MAX_SERIALS: usize = 4;
Jiyong Park00ceff32023-03-13 05:43:23 +0000401}
402
Jiyong Park6a8789a2023-03-21 14:50:59 +0900403fn read_serial_info_from(fdt: &Fdt) -> libfdt::Result<SerialInfo> {
404 let mut addrs: ArrayVec<[u64; SerialInfo::MAX_SERIALS]> = Default::default();
405 for node in fdt.compatible_nodes(cstr!("ns16550a"))?.take(SerialInfo::MAX_SERIALS) {
406 let reg = node.reg()?.ok_or(FdtError::NotFound)?.next().ok_or(FdtError::NotFound)?;
407 addrs.push(reg.addr);
Jiyong Park00ceff32023-03-13 05:43:23 +0000408 }
Jiyong Park6a8789a2023-03-21 14:50:59 +0900409 Ok(SerialInfo { addrs })
Jiyong Park00ceff32023-03-13 05:43:23 +0000410}
411
Jiyong Park9c63cd12023-03-21 17:53:07 +0900412/// Patch the DT by deleting the ns16550a compatible nodes whose address are unknown
413fn patch_serial_info(fdt: &mut Fdt, serial_info: &SerialInfo) -> libfdt::Result<()> {
414 let name = cstr!("ns16550a");
415 let mut next = fdt.root_mut()?.next_compatible(name);
416 while let Some(current) = next? {
417 let reg = FdtNode::from_mut(&current)
418 .reg()?
419 .ok_or(FdtError::NotFound)?
420 .next()
421 .ok_or(FdtError::NotFound)?;
422 next = if !serial_info.addrs.contains(&reg.addr) {
423 current.delete_and_next_compatible(name)
424 } else {
425 current.next_compatible(name)
426 }
427 }
428 Ok(())
429}
430
Jiyong Park00ceff32023-03-13 05:43:23 +0000431#[derive(Debug)]
Jiyong Park6a8789a2023-03-21 14:50:59 +0900432struct SwiotlbInfo {
Jiyong Park00ceff32023-03-13 05:43:23 +0000433 size: u64,
434 align: u64,
435}
436
Jiyong Park6a8789a2023-03-21 14:50:59 +0900437fn read_swiotlb_info_from(fdt: &Fdt) -> libfdt::Result<SwiotlbInfo> {
438 let node =
439 fdt.compatible_nodes(cstr!("restricted-dma-pool"))?.next().ok_or(FdtError::NotFound)?;
440 let size = node.getprop_u64(cstr!("size"))?.ok_or(FdtError::NotFound)?;
441 let align = node.getprop_u64(cstr!("alignment"))?.ok_or(FdtError::NotFound)?;
442 Ok(SwiotlbInfo { size, align })
443}
Jiyong Park00ceff32023-03-13 05:43:23 +0000444
Jiyong Park6a8789a2023-03-21 14:50:59 +0900445fn validate_swiotlb_info(swiotlb_info: &SwiotlbInfo) -> Result<(), RebootReason> {
446 let size = swiotlb_info.size;
447 let align = swiotlb_info.align;
Jiyong Park00ceff32023-03-13 05:43:23 +0000448
449 if size == 0 || (size % GUEST_PAGE_SIZE as u64) != 0 {
450 error!("Invalid swiotlb size {:#x}", size);
451 return Err(RebootReason::InvalidFdt);
452 }
453
454 if (align % GUEST_PAGE_SIZE as u64) != 0 {
455 error!("Invalid swiotlb alignment {:#x}", align);
456 return Err(RebootReason::InvalidFdt);
457 }
Jiyong Park6a8789a2023-03-21 14:50:59 +0900458 Ok(())
Jiyong Park00ceff32023-03-13 05:43:23 +0000459}
460
Jiyong Park9c63cd12023-03-21 17:53:07 +0900461fn patch_swiotlb_info(fdt: &mut Fdt, swiotlb_info: &SwiotlbInfo) -> libfdt::Result<()> {
462 let mut node =
463 fdt.root_mut()?.next_compatible(cstr!("restricted-dma-pool"))?.ok_or(FdtError::NotFound)?;
464 node.setprop_inplace(cstr!("size"), &swiotlb_info.size.to_be_bytes())?;
465 node.setprop_inplace(cstr!("alignment"), &swiotlb_info.align.to_be_bytes())?;
466 Ok(())
467}
468
469fn patch_gic(fdt: &mut Fdt, num_cpus: usize) -> libfdt::Result<()> {
470 let node = fdt.compatible_nodes(cstr!("arm,gic-v3"))?.next().ok_or(FdtError::NotFound)?;
471 let mut ranges = node.reg()?.ok_or(FdtError::NotFound)?;
472 let range0 = ranges.next().ok_or(FdtError::NotFound)?;
473 let mut range1 = ranges.next().ok_or(FdtError::NotFound)?;
474
475 let addr = range0.addr;
476 // SAFETY - doesn't overflow. checked in validate_num_cpus
477 let size: u64 =
478 DeviceTreeInfo::GIC_REDIST_SIZE_PER_CPU.checked_mul(num_cpus.try_into().unwrap()).unwrap();
479
480 // range1 is just below range0
481 range1.addr = addr - size;
482 range1.size = Some(size);
483
484 let range0 = range0.to_cells();
485 let range1 = range1.to_cells();
486 let value = [
487 range0.0, // addr
488 range0.1.unwrap(), //size
489 range1.0, // addr
490 range1.1.unwrap(), //size
491 ];
492
493 let mut node =
494 fdt.root_mut()?.next_compatible(cstr!("arm,gic-v3"))?.ok_or(FdtError::NotFound)?;
495 node.setprop_inplace(cstr!("reg"), flatten(&value))
496}
497
498fn patch_timer(fdt: &mut Fdt, num_cpus: usize) -> libfdt::Result<()> {
499 const NUM_INTERRUPTS: usize = 4;
500 const CELLS_PER_INTERRUPT: usize = 3;
501 let node = fdt.compatible_nodes(cstr!("arm,armv8-timer"))?.next().ok_or(FdtError::NotFound)?;
502 let interrupts = node.getprop_cells(cstr!("interrupts"))?.ok_or(FdtError::NotFound)?;
503 let mut value: ArrayVec<[u32; NUM_INTERRUPTS * CELLS_PER_INTERRUPT]> =
504 interrupts.take(NUM_INTERRUPTS * CELLS_PER_INTERRUPT).collect();
505
506 let num_cpus: u32 = num_cpus.try_into().unwrap();
507 let cpu_mask: u32 = (((0x1 << num_cpus) - 1) & 0xff) << 8;
508 for v in value.iter_mut().skip(2).step_by(CELLS_PER_INTERRUPT) {
509 *v |= cpu_mask;
510 }
511 for v in value.iter_mut() {
512 *v = v.to_be();
513 }
514
515 // SAFETY - array size is the same
516 let value = unsafe {
517 core::mem::transmute::<
518 [u32; NUM_INTERRUPTS * CELLS_PER_INTERRUPT],
519 [u8; NUM_INTERRUPTS * CELLS_PER_INTERRUPT * size_of::<u32>()],
520 >(value.into_inner())
521 };
522
523 let mut node =
524 fdt.root_mut()?.next_compatible(cstr!("arm,armv8-timer"))?.ok_or(FdtError::NotFound)?;
525 node.setprop_inplace(cstr!("interrupts"), value.as_slice())
526}
527
Jiyong Park00ceff32023-03-13 05:43:23 +0000528#[derive(Debug)]
Jiyong Park6a8789a2023-03-21 14:50:59 +0900529pub struct DeviceTreeInfo {
530 pub kernel_range: Option<Range<usize>>,
531 pub initrd_range: Option<Range<usize>>,
532 pub memory_range: Range<usize>,
Jiyong Parke9d87e82023-03-21 19:28:40 +0900533 bootargs: Option<CString>,
Jiyong Park6a8789a2023-03-21 14:50:59 +0900534 num_cpus: usize,
Jiyong Park00ceff32023-03-13 05:43:23 +0000535 pci_info: PciInfo,
536 serial_info: SerialInfo,
537 swiotlb_info: SwiotlbInfo,
538}
539
540impl DeviceTreeInfo {
Jiyong Park9c63cd12023-03-21 17:53:07 +0900541 const GIC_REDIST_SIZE_PER_CPU: u64 = (32 * SIZE_4KB) as u64;
Jiyong Park00ceff32023-03-13 05:43:23 +0000542}
543
Jiyong Park9c63cd12023-03-21 17:53:07 +0900544pub fn sanitize_device_tree(fdt: &mut Fdt) -> Result<DeviceTreeInfo, RebootReason> {
Jiyong Park83316122023-03-21 09:39:39 +0900545 let info = parse_device_tree(fdt)?;
546 debug!("Device tree info: {:?}", info);
547
Jiyong Parke9d87e82023-03-21 19:28:40 +0900548 fdt.copy_from_slice(pvmfw_fdt_template::RAW).map_err(|e| {
549 error!("Failed to instantiate FDT from the template DT: {e}");
550 RebootReason::InvalidFdt
551 })?;
552
Jiyong Park9c63cd12023-03-21 17:53:07 +0900553 patch_device_tree(fdt, &info)?;
Jiyong Park6a8789a2023-03-21 14:50:59 +0900554 Ok(info)
Jiyong Park83316122023-03-21 09:39:39 +0900555}
556
557fn parse_device_tree(fdt: &libfdt::Fdt) -> Result<DeviceTreeInfo, RebootReason> {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900558 let kernel_range = read_kernel_range_from(fdt).map_err(|e| {
559 error!("Failed to read kernel range from DT: {e}");
560 RebootReason::InvalidFdt
561 })?;
562
563 let initrd_range = read_initrd_range_from(fdt).map_err(|e| {
564 error!("Failed to read initrd range from DT: {e}");
565 RebootReason::InvalidFdt
566 })?;
567
568 let memory_range = read_memory_range_from(fdt).map_err(|e| {
569 error!("Failed to read memory range from DT: {e}");
570 RebootReason::InvalidFdt
571 })?;
572 validate_memory_range(&memory_range)?;
573
Jiyong Parke9d87e82023-03-21 19:28:40 +0900574 let bootargs = read_bootargs_from(fdt).map_err(|e| {
575 error!("Failed to read bootargs from DT: {e}");
576 RebootReason::InvalidFdt
577 })?;
578
Jiyong Park6a8789a2023-03-21 14:50:59 +0900579 let num_cpus = read_num_cpus_from(fdt).map_err(|e| {
580 error!("Failed to read num cpus from DT: {e}");
581 RebootReason::InvalidFdt
582 })?;
583 validate_num_cpus(num_cpus)?;
584
585 let pci_info = read_pci_info_from(fdt).map_err(|e| {
586 error!("Failed to read pci info from DT: {e}");
587 RebootReason::InvalidFdt
588 })?;
Jiyong Park0ee65392023-03-27 20:52:45 +0900589 validate_pci_info(&pci_info, &memory_range)?;
Jiyong Park6a8789a2023-03-21 14:50:59 +0900590
591 let serial_info = read_serial_info_from(fdt).map_err(|e| {
592 error!("Failed to read serial info from DT: {e}");
593 RebootReason::InvalidFdt
594 })?;
595
596 let swiotlb_info = read_swiotlb_info_from(fdt).map_err(|e| {
597 error!("Failed to read swiotlb info from DT: {e}");
598 RebootReason::InvalidFdt
599 })?;
600 validate_swiotlb_info(&swiotlb_info)?;
601
Jiyong Park00ceff32023-03-13 05:43:23 +0000602 Ok(DeviceTreeInfo {
Jiyong Park6a8789a2023-03-21 14:50:59 +0900603 kernel_range,
604 initrd_range,
605 memory_range,
Jiyong Parke9d87e82023-03-21 19:28:40 +0900606 bootargs,
Jiyong Park6a8789a2023-03-21 14:50:59 +0900607 num_cpus,
608 pci_info,
609 serial_info,
610 swiotlb_info,
Jiyong Park00ceff32023-03-13 05:43:23 +0000611 })
612}
613
Jiyong Park9c63cd12023-03-21 17:53:07 +0900614fn patch_device_tree(fdt: &mut Fdt, info: &DeviceTreeInfo) -> Result<(), RebootReason> {
Jiyong Parke9d87e82023-03-21 19:28:40 +0900615 fdt.unpack().map_err(|e| {
616 error!("Failed to unpack DT for patching: {e}");
617 RebootReason::InvalidFdt
618 })?;
619
Jiyong Park9c63cd12023-03-21 17:53:07 +0900620 if let Some(initrd_range) = &info.initrd_range {
621 patch_initrd_range(fdt, initrd_range).map_err(|e| {
622 error!("Failed to patch initrd range to DT: {e}");
623 RebootReason::InvalidFdt
624 })?;
625 }
626 patch_memory_range(fdt, &info.memory_range).map_err(|e| {
627 error!("Failed to patch memory range to DT: {e}");
628 RebootReason::InvalidFdt
629 })?;
Jiyong Parke9d87e82023-03-21 19:28:40 +0900630 if let Some(bootargs) = &info.bootargs {
631 patch_bootargs(fdt, bootargs.as_c_str()).map_err(|e| {
632 error!("Failed to patch bootargs to DT: {e}");
633 RebootReason::InvalidFdt
634 })?;
635 }
Jiyong Park9c63cd12023-03-21 17:53:07 +0900636 patch_num_cpus(fdt, info.num_cpus).map_err(|e| {
637 error!("Failed to patch cpus to DT: {e}");
638 RebootReason::InvalidFdt
639 })?;
640 patch_pci_info(fdt, &info.pci_info).map_err(|e| {
641 error!("Failed to patch pci info to DT: {e}");
642 RebootReason::InvalidFdt
643 })?;
644 patch_serial_info(fdt, &info.serial_info).map_err(|e| {
645 error!("Failed to patch serial info to DT: {e}");
646 RebootReason::InvalidFdt
647 })?;
648 patch_swiotlb_info(fdt, &info.swiotlb_info).map_err(|e| {
649 error!("Failed to patch swiotlb info to DT: {e}");
650 RebootReason::InvalidFdt
651 })?;
652 patch_gic(fdt, info.num_cpus).map_err(|e| {
653 error!("Failed to patch gic info to DT: {e}");
654 RebootReason::InvalidFdt
655 })?;
656 patch_timer(fdt, info.num_cpus).map_err(|e| {
657 error!("Failed to patch timer info to DT: {e}");
658 RebootReason::InvalidFdt
659 })?;
Jiyong Parke9d87e82023-03-21 19:28:40 +0900660
661 fdt.pack().map_err(|e| {
662 error!("Failed to pack DT after patching: {e}");
663 RebootReason::InvalidFdt
664 })?;
665
Jiyong Park9c63cd12023-03-21 17:53:07 +0900666 Ok(())
667}
668
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000669/// Modifies the input DT according to the fields of the configuration.
670pub fn modify_for_next_stage(
671 fdt: &mut Fdt,
672 bcc: &[u8],
673 new_instance: bool,
674 strict_boot: bool,
675) -> libfdt::Result<()> {
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000676 fdt.unpack()?;
677
Jiyong Parke9d87e82023-03-21 19:28:40 +0900678 patch_dice_node(fdt, bcc.as_ptr() as usize, bcc.len())?;
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000679
Jiyong Parkb87f3302023-03-21 10:03:11 +0900680 set_or_clear_chosen_flag(fdt, cstr!("avf,strict-boot"), strict_boot)?;
681 set_or_clear_chosen_flag(fdt, cstr!("avf,new-instance"), new_instance)?;
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000682
683 fdt.pack()?;
684
685 Ok(())
686}
687
Jiyong Parke9d87e82023-03-21 19:28:40 +0900688/// Patch the "google,open-dice"-compatible reserved-memory node to point to the bcc range
689fn patch_dice_node(fdt: &mut Fdt, addr: usize, size: usize) -> libfdt::Result<()> {
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000690 // We reject DTs with missing reserved-memory node as validation should have checked that the
691 // "swiotlb" subnode (compatible = "restricted-dma-pool") was present.
Jiyong Parke9d87e82023-03-21 19:28:40 +0900692 let node = fdt.node_mut(cstr!("/reserved-memory"))?.ok_or(libfdt::FdtError::NotFound)?;
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000693
Jiyong Parke9d87e82023-03-21 19:28:40 +0900694 let mut node = node.next_compatible(cstr!("google,open-dice"))?.ok_or(FdtError::NotFound)?;
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000695
Jiyong Parke9d87e82023-03-21 19:28:40 +0900696 let addr: u64 = addr.try_into().unwrap();
697 let size: u64 = size.try_into().unwrap();
698 node.setprop_inplace(cstr!("reg"), flatten(&[addr.to_be_bytes(), size.to_be_bytes()]))
Pierre-Clément Tosi4ba79662023-02-13 11:22:41 +0000699}
700
701fn set_or_clear_chosen_flag(fdt: &mut Fdt, flag: &CStr, value: bool) -> libfdt::Result<()> {
702 // TODO(b/249054080): Refactor to not panic if the DT doesn't contain a /chosen node.
703 let mut chosen = fdt.chosen_mut()?.unwrap();
704 if value {
705 chosen.setprop_empty(flag)?;
706 } else {
707 match chosen.delprop(flag) {
708 Ok(()) | Err(FdtError::NotFound) => (),
709 Err(e) => return Err(e),
710 }
711 }
Pierre-Clément Tosidb74cb12022-12-08 13:56:25 +0000712
713 Ok(())
714}