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Alice Wang81399f52023-05-26 14:23:43 +00001// Copyright 2023, The Android Open Source Project
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
15//! Wrappers of assembly calls.
16
Michał Mazurekf08509a2025-01-24 11:39:24 +000017pub mod layout;
Michał Mazurek6cd065f2024-11-29 13:07:11 +010018pub mod linker;
Michał Mazurek5b294692024-11-29 13:05:46 +010019pub mod page_table;
Bartłomiej Grzesik86f108d2024-11-29 15:48:00 +010020pub mod platform;
21
Alice Wang81399f52023-05-26 14:23:43 +000022/// Reads a value from a system register.
23#[macro_export]
24macro_rules! read_sysreg {
25 ($sysreg:literal) => {{
26 let mut r: usize;
Alice Wang81399f52023-05-26 14:23:43 +000027 #[allow(unused_unsafe)] // In case the macro is used within an unsafe block.
Andrew Walbranc06e7342023-07-05 14:00:51 +000028 // SAFETY: Reading a system register does not affect memory.
Alice Wang81399f52023-05-26 14:23:43 +000029 unsafe {
30 core::arch::asm!(
31 concat!("mrs {}, ", $sysreg),
32 out(reg) r,
33 options(nomem, nostack, preserves_flags),
34 )
35 }
36 r
37 }};
38}
39
40/// Writes a value to a system register.
41///
42/// # Safety
43///
44/// Callers must ensure that side effects of updating the system register are properly handled.
45#[macro_export]
46macro_rules! write_sysreg {
47 ($sysreg:literal, $val:expr) => {{
48 let value: usize = $val;
49 core::arch::asm!(
50 concat!("msr ", $sysreg, ", {}"),
51 in(reg) value,
52 options(nomem, nostack, preserves_flags),
53 )
54 }};
55}
56
57/// Executes an instruction synchronization barrier.
58#[macro_export]
59macro_rules! isb {
60 () => {{
Alice Wang81399f52023-05-26 14:23:43 +000061 #[allow(unused_unsafe)] // In case the macro is used within an unsafe block.
Andrew Walbranc06e7342023-07-05 14:00:51 +000062 // SAFETY: memory barriers do not affect Rust's memory model.
Alice Wang81399f52023-05-26 14:23:43 +000063 unsafe {
64 core::arch::asm!("isb", options(nomem, nostack, preserves_flags));
65 }
66 }};
67}
68
69/// Executes a data synchronization barrier.
70#[macro_export]
71macro_rules! dsb {
72 ($option:literal) => {{
Alice Wang81399f52023-05-26 14:23:43 +000073 #[allow(unused_unsafe)] // In case the macro is used within an unsafe block.
Andrew Walbranc06e7342023-07-05 14:00:51 +000074 // SAFETY: memory barriers do not affect Rust's memory model.
Alice Wang81399f52023-05-26 14:23:43 +000075 unsafe {
76 core::arch::asm!(concat!("dsb ", $option), options(nomem, nostack, preserves_flags));
77 }
78 }};
79}
80
Pierre-Clément Tosi8ab7c372024-10-30 20:46:04 +000081/// Executes a data cache operation.
82#[macro_export]
83macro_rules! dc {
84 ($option:literal, $addr:expr) => {{
85 let addr: usize = $addr;
86 #[allow(unused_unsafe)] // In case the macro is used within an unsafe block.
87 // SAFETY: Clearing cache lines shouldn't have Rust-visible side effects.
88 unsafe {
89 core::arch::asm!(
90 concat!("dc ", $option, ", {x}"),
91 x = in(reg) addr,
92 options(nomem, nostack, preserves_flags),
93 );
94 }
95 }};
96}
97
Alice Wang81399f52023-05-26 14:23:43 +000098/// Invalidates cached leaf PTE entries by virtual address.
99#[macro_export]
100macro_rules! tlbi {
101 ($option:literal, $asid:expr, $addr:expr) => {{
102 let asid: usize = $asid;
103 let addr: usize = $addr;
Alice Wang81399f52023-05-26 14:23:43 +0000104 #[allow(unused_unsafe)] // In case the macro is used within an unsafe block.
Andrew Walbranc06e7342023-07-05 14:00:51 +0000105 // SAFETY: Invalidating the TLB doesn't affect Rust. When the address matches a
106 // block entry larger than the page size, all translations for the block are invalidated.
Alice Wang81399f52023-05-26 14:23:43 +0000107 unsafe {
108 core::arch::asm!(
109 concat!("tlbi ", $option, ", {x}"),
110 x = in(reg) (asid << 48) | (addr >> 12),
111 options(nomem, nostack, preserves_flags)
112 );
113 }
114 }};
115}
Pierre-Clément Tosi4ec3a932024-10-08 18:10:25 +0100116
Pierre-Clément Tosi043dfb72024-10-30 21:17:10 +0000117/// STRB intrinsics.
Pierre-Clément Tosi4ec3a932024-10-08 18:10:25 +0100118///
119/// See https://github.com/rust-lang/rust/issues/131894
120///
121/// # Safety
122///
123/// `dst` must be valid for writes.
Pierre-Clément Tosi043dfb72024-10-30 21:17:10 +0000124#[inline]
125pub unsafe fn strb(dst: *mut u8, src: u8) {
Pierre-Clément Tosi4ec3a932024-10-08 18:10:25 +0100126 // SAFETY: strb only modifies *dst, which must be valid for writes.
127 unsafe {
128 core::arch::asm!(
129 "strb {value:w}, [{ptr}]",
130 value = in(reg) src,
131 ptr = in(reg) dst,
132 options(preserves_flags),
133 );
134 }
135}
Pierre-Clément Tosi8ab7c372024-10-30 20:46:04 +0000136
137/// Reads the number of words in the smallest cache line of all the data caches and unified caches.
138#[inline]
139pub fn min_dcache_line_size() -> usize {
140 const DMINLINE_SHIFT: usize = 16;
141 const DMINLINE_MASK: usize = 0xf;
142 let ctr_el0 = read_sysreg!("ctr_el0");
143
144 // DminLine: log2 of the number of words in the smallest cache line of all the data caches.
145 let dminline = (ctr_el0 >> DMINLINE_SHIFT) & DMINLINE_MASK;
146
147 1 << dminline
148}