diff --git a/vmbase/src/memory/mod.rs b/vmbase/src/memory/mod.rs
index 13f1af5..bb9149c 100644
--- a/vmbase/src/memory/mod.rs
+++ b/vmbase/src/memory/mod.rs
@@ -20,7 +20,7 @@
 mod util;
 
 pub use dbm::{flush_dirty_range, set_dbm_enabled};
-pub use page_table::{is_leaf_pte, PageTable, MMIO_LAZY_MAP_FLAG};
+pub use page_table::{is_leaf_pte, PageTable, MMIO_LAZY_MAP_FLAG, PT_ASID};
 pub use shared::MemorySharer;
 pub use util::{
     flush, flushed_zeroize, min_dcache_line_size, page_4kb_of, phys_to_virt, virt_to_phys,
diff --git a/vmbase/src/memory/page_table.rs b/vmbase/src/memory/page_table.rs
index d3564b6..1a9d0f8 100644
--- a/vmbase/src/memory/page_table.rs
+++ b/vmbase/src/memory/page_table.rs
@@ -35,6 +35,12 @@
 const RODATA: Attributes = DATA.union(Attributes::READ_ONLY);
 const DATA_DBM: Attributes = RODATA.union(Attributes::DBM);
 
+/// Root level is given by the value of TCR_EL1.TG0 and TCR_EL1.T0SZ, set in
+/// entry.S. For 4KB granule and 39-bit VA, the root level is 1.
+const PT_ROOT_LEVEL: usize = 1;
+/// Page table ASID.
+pub const PT_ASID: usize = 1;
+
 type Result<T> = result::Result<T, MapError>;
 
 /// High-level API for managing MMU mappings.
@@ -48,6 +54,12 @@
     }
 }
 
+impl Default for PageTable {
+    fn default() -> Self {
+        IdMap::new(PT_ASID, PT_ROOT_LEVEL).into()
+    }
+}
+
 impl PageTable {
     /// Activates the page table.
     ///