[virtio] Move virtio module from pvmfw to vmbase
for reuse in both pvmfw and rialo.
No code change in this cl.
Bug: 284462758
Test: m pvmfw_img
Change-Id: I225b495a2f8c1a49cb63ea69d60f01949bab3f05
diff --git a/pvmfw/src/gpt.rs b/pvmfw/src/gpt.rs
index e0ffdc3..b553705 100644
--- a/pvmfw/src/gpt.rs
+++ b/pvmfw/src/gpt.rs
@@ -14,7 +14,6 @@
//! Support for parsing GUID partition tables.
-use crate::virtio::pci::VirtIOBlk;
use core::cmp::min;
use core::fmt;
use core::mem::size_of;
@@ -25,6 +24,7 @@
use uuid::Uuid;
use virtio_drivers::device::blk::SECTOR_SIZE;
use vmbase::util::ceiling_div;
+use vmbase::virtio::pci::VirtIOBlk;
use zerocopy::FromBytes;
pub enum Error {
diff --git a/pvmfw/src/instance.rs b/pvmfw/src/instance.rs
index 9a6a6e4..b96ae1e 100644
--- a/pvmfw/src/instance.rs
+++ b/pvmfw/src/instance.rs
@@ -22,7 +22,6 @@
use crate::gpt::Partition;
use crate::gpt::Partitions;
use crate::rand;
-use crate::virtio::pci::VirtIOBlkIterator;
use core::fmt;
use core::mem::size_of;
use diced_open_dice::DiceMode;
@@ -32,6 +31,7 @@
use uuid::Uuid;
use virtio_drivers::transport::pci::bus::PciRoot;
use vmbase::util::ceiling_div;
+use vmbase::virtio::pci::VirtIOBlkIterator;
use zerocopy::AsBytes;
use zerocopy::FromBytes;
diff --git a/pvmfw/src/main.rs b/pvmfw/src/main.rs
index c6baf6d..c826cd8 100644
--- a/pvmfw/src/main.rs
+++ b/pvmfw/src/main.rs
@@ -34,7 +34,6 @@
mod instance;
mod memory;
mod rand;
-mod virtio;
use crate::bcc::Bcc;
use crate::dice::PartialInputs;
@@ -42,7 +41,6 @@
use crate::fdt::modify_for_next_stage;
use crate::helpers::GUEST_PAGE_SIZE;
use crate::instance::get_or_generate_instance_salt;
-use crate::virtio::pci;
use alloc::boxed::Box;
use core::ops::Range;
use diced_open_dice::{bcc_handover_parse, DiceArtifacts};
@@ -55,6 +53,7 @@
use pvmfw_embedded_key::PUBLIC_KEY;
use vmbase::memory::flush;
use vmbase::memory::MEMORY;
+use vmbase::virtio::pci;
const NEXT_BCC_SIZE: usize = GUEST_PAGE_SIZE;
diff --git a/vmbase/Android.bp b/vmbase/Android.bp
index 6420b2b..6db9ff8 100644
--- a/vmbase/Android.bp
+++ b/vmbase/Android.bp
@@ -65,12 +65,14 @@
rustlibs: [
"libaarch64_paging",
"libbuddy_system_allocator",
+ "libfdtpci",
"libhyp",
"liblog_rust_nostd",
"libonce_cell_nostd",
"libsmccc",
"libspin_nostd",
"libtinyvec_nostd",
+ "libvirtio_drivers",
"libzeroize_nostd",
],
whole_static_libs: [
diff --git a/vmbase/src/lib.rs b/vmbase/src/lib.rs
index 80cdf4e..ebb3707 100644
--- a/vmbase/src/lib.rs
+++ b/vmbase/src/lib.rs
@@ -29,6 +29,7 @@
pub mod power;
pub mod uart;
pub mod util;
+pub mod virtio;
pub use bionic::STACK_CHK_GUARD;
diff --git a/pvmfw/src/virtio/hal.rs b/vmbase/src/virtio/hal.rs
similarity index 96%
rename from pvmfw/src/virtio/hal.rs
rename to vmbase/src/virtio/hal.rs
index f223a7e..ac5b967 100644
--- a/pvmfw/src/virtio/hal.rs
+++ b/vmbase/src/virtio/hal.rs
@@ -15,13 +15,13 @@
//! HAL for the virtio_drivers crate.
use super::pci::PCI_INFO;
+use crate::memory::{alloc_shared, dealloc_shared, phys_to_virt, virt_to_phys};
+use crate::util::RangeExt as _;
use core::alloc::Layout;
use core::mem::size_of;
use core::ptr::{copy_nonoverlapping, NonNull};
use log::trace;
use virtio_drivers::{BufferDirection, Hal, PhysAddr, PAGE_SIZE};
-use vmbase::memory::{alloc_shared, dealloc_shared, phys_to_virt, virt_to_phys};
-use vmbase::util::RangeExt as _;
/// The alignment to use for the temporary buffers allocated by `HalImpl::share`. There doesn't seem
/// to be any particular alignment required by VirtIO for these, so 16 bytes should be enough to
@@ -29,6 +29,7 @@
/// alignment to the memory sharing granule size anyway.
const SHARED_BUFFER_ALIGNMENT: usize = size_of::<u128>();
+/// HAL implementation for the virtio_drivers crate.
pub struct HalImpl;
/// # Safety
diff --git a/pvmfw/src/virtio.rs b/vmbase/src/virtio/mod.rs
similarity index 100%
rename from pvmfw/src/virtio.rs
rename to vmbase/src/virtio/mod.rs
diff --git a/pvmfw/src/virtio/pci.rs b/vmbase/src/virtio/pci.rs
similarity index 96%
rename from pvmfw/src/virtio/pci.rs
rename to vmbase/src/virtio/pci.rs
index fd99c07..b54f7d1 100644
--- a/pvmfw/src/virtio/pci.rs
+++ b/vmbase/src/virtio/pci.rs
@@ -15,6 +15,7 @@
//! Functions to scan the PCI bus for VirtIO devices.
use super::hal::HalImpl;
+use crate::memory::{MemoryTracker, MemoryTrackerError};
use alloc::boxed::Box;
use core::fmt;
use fdtpci::PciInfo;
@@ -30,7 +31,6 @@
DeviceType, Transport,
},
};
-use vmbase::memory::{MemoryTracker, MemoryTrackerError};
pub(super) static PCI_INFO: OnceBox<PciInfo> = OnceBox::new();
@@ -78,14 +78,17 @@
Ok(unsafe { pci_info.make_pci_root() })
}
+/// Virtio Block device.
pub type VirtIOBlk = blk::VirtIOBlk<HalImpl, PciTransport>;
+/// Virtio Block device iterator.
pub struct VirtIOBlkIterator<'a> {
pci_root: &'a mut PciRoot,
bus: BusDeviceIterator,
}
impl<'a> VirtIOBlkIterator<'a> {
+ /// Creates a new iterator.
pub fn new(pci_root: &'a mut PciRoot) -> Self {
let bus = pci_root.enumerate_bus(0);
Self { pci_root, bus }