[rialto] Parse the PCI info from rialto's device tree
This is the first part of the change to enable access
to a virtio socket device via the PCI bus in rialto.
Bug: 282928116
Test: atest rialto_test
Change-Id: Ia7979f45f3ed565ce185bf337211740f74ebee2c
diff --git a/rialto/src/error.rs b/rialto/src/error.rs
index 754e554..bf26639 100644
--- a/rialto/src/error.rs
+++ b/rialto/src/error.rs
@@ -16,7 +16,9 @@
use aarch64_paging::MapError;
use core::{fmt, result};
+use fdtpci::PciError;
use hyp::Error as HypervisorError;
+use libfdt::FdtError;
pub type Result<T> = result::Result<T, Error>;
@@ -28,16 +30,22 @@
PageTableMapping(MapError),
/// Failed to initialize the logger.
LoggerInit,
+ /// Invalid FDT.
+ InvalidFdt(FdtError),
+ /// Invalid PCI.
+ InvalidPci(PciError),
}
impl fmt::Display for Error {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
match self {
- Self::Hypervisor(e) => write!(f, "MMIO guard failed: {e}."),
+ Self::Hypervisor(e) => write!(f, "Hypervisor error: {e}."),
Self::PageTableMapping(e) => {
write!(f, "Failed when attempting to map some range in the page table: {e}.")
}
Self::LoggerInit => write!(f, "Failed to initialize the logger."),
+ Self::InvalidFdt(e) => write!(f, "Invalid FDT: {e}"),
+ Self::InvalidPci(e) => write!(f, "Invalid PCI: {e}"),
}
}
}
@@ -53,3 +61,15 @@
Self::PageTableMapping(e)
}
}
+
+impl From<FdtError> for Error {
+ fn from(e: FdtError) -> Self {
+ Self::InvalidFdt(e)
+ }
+}
+
+impl From<PciError> for Error {
+ fn from(e: PciError) -> Self {
+ Self::InvalidPci(e)
+ }
+}