)]}'
{
  "commit": "b51bd6f6114b46540c2923b4ac5189a4065f820b",
  "tree": "8a43a43c97ec01376f3e6d694b0b30ff37877cde",
  "parents": [
    "66dd4fed98448d97b999af8f0e3b54a0f099b9a5"
  ],
  "author": {
    "name": "Jiyong Park",
    "email": "jiyong@google.com",
    "time": "Tue Oct 18 13:30:52 2022 +0900"
  },
  "committer": {
    "name": "Jiyong Park",
    "email": "jiyong@google.com",
    "time": "Tue Oct 18 13:30:52 2022 +0900"
  },
  "message": "Update kernel to builds 9186328\n\ngit log --first-parent -100 --oneline --no-decorate f1076051b3e9..116049110fe9:\n116049110fe9 UPSTREAM: KVM: arm64: Enable stack protection and branch profiling for VHE\ne2130dcc2740 UPSTREAM: KVM: arm64: Limit stage2_apply_range() batch size to largest block\nc3feb623e558 UPSTREAM: KVM: arm64: Work out supported block level at compile time\n7a3109b88269 UPSTREAM: KVM: arm64: Advertise new kvmarm mailing list\n333ef9056d7d UPSTREAM: KVM: arm64: Fix comment typo in nvhe/switch.c\nfbfb98ef79db UPSTREAM: KVM: arm64: Ignore kvm-arm.mode if !is_hyp_mode_available()\nb0adfe8951a8 UPSTREAM: KVM: arm64: vgic: Remove duplicate check in update_affinity_collection()\n6b54405d184b UPSTREAM: KVM: arm64: Clear PSTATE.SS when the Software Step state was Active-pending\nbf409da6ab78 UPSTREAM: KVM: arm64: Preserve PSTATE.SS for the guest while single-step is enabled\na9758c12946e UPSTREAM: arm64/sysreg: Use feature numbering for PMU and SPE revisions\n088a7845221a UPSTREAM: KVM: arm64: Treat 32bit ID registers as RAZ/WI on 64bit-only system\n983d6d3ff15b UPSTREAM: KVM: arm64: Add a visibility bit to ignore user writes\nd3ba4ecf56d0 UPSTREAM: KVM: arm64: Spin off helper for calling visibility hook\nb6560dc8eb53 BACKPORT: KVM: arm64: Drop raz parameter from read_id_reg()\nc10b44010f0d UPSTREAM: KVM: arm64: Remove internal accessor helpers for id regs\n3299232ccff4 UPSTREAM: KVM: arm64: Use visibility hook to treat ID regs as RAZ\nd01fe592078c BACKPORT: arm64: cache: Remove unused CTR_CACHE_MINLINE_MASK\n3130e8d2c935 UPSTREAM: arm64/sysreg: Fix a few missed conversions\nd6a1f7790572 UPSTREAM: arm64/sysreg: Add _EL1 into ID_AA64DFR0_EL1 definition names\n4324ec29f654 UPSTREAM: arm64/sysreg: Align field names in ID_AA64DFR0_EL1 with architecture\nc023354bb307 UPSTREAM: arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 SME enumeration\n0790b96bc276 UPSTREAM: arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 BTI enumeration\nfd6970e8123f UPSTREAM: arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 fractional version fields\n76eac5d39473 UPSTREAM: arm64/sysreg: Standardise naming for MTE feature enumeration\n09e8085abe9e UPSTREAM: arm64/sysreg: Standardise naming for SSBS feature enumeration\na28f8e2ec6b4 UPSTREAM: arm64/sysreg: Standardise naming for ID_AA64PFR0_EL1.AdvSIMD constants\n48bcf915c0f5 UPSTREAM: arm64/sysreg: Standardise naming for ID_AA64PFR0_EL1 constants\n510b36408e5d UPSTREAM: arm64/sysreg: Standardise naming for ID_AA64MMFR2_EL1.CnP\nbd568d48d365 BACKPORT: arm64/sysreg: Standardise naming for ID_AA64MMFR2_EL1.VARange\n89388ad4f49e BACKPORT: arm64/sysreg: Standardise naming for ID_AA64MMFR1_EL1 fields\n475c494b5d5d UPSTREAM: arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.ASIDBits\n665c8a7a28a9 UPSTREAM: arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.BigEnd\n44fc6ed1b20d BACKPORT: arm64/sysreg: Add _EL1 into ID_AA64PFR1_EL1 constant names\n71e184180a5d BACKPORT: arm64/sysreg: Add _EL1 into ID_AA64PFR0_EL1 definition names\n0cb0fd4d2f6b BACKPORT: arm64/sysreg: Add _EL1 into ID_AA64MMFR2_EL1 definition names\ndef82c15a779 BACKPORT: arm64/sysreg: Add _EL1 into ID_AA64MMFR0_EL1 definition names\n61157226850c UPSTREAM: arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names\n0994f3c72a34 UPSTREAM: arm64/sysreg: Make BHB clear feature defines match the architecture\na8d83396fdb5 BACKPORT: arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names\n8941f2e9f0ee UPSTREAM: arm64/idreg: Fix tab/space damage\n2796fe818d58 UPSTREAM: arm64/sysreg: Align pointer auth enumeration defines with architecture\n0def03eb82a3 UPSTREAM: arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields\n3ffaa9a1b0a0 UPSTREAM: arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums\nbf808e9dca60 UPSTREAM: arm64/sme: Fix tests for 0b1111 value ID registers\n6e316bd046ba UPSTREAM: arm64/sysreg: Standardise naming for WFxT defines\ndc164e3eb420 UPSTREAM: arm64/mte: Standardise GMID field name definitions\nbb12726e3445 UPSTREAM: arm64/sysreg: Standardise naming for DCZID_EL0 field names\nf660cd96148d BACKPORT: arm64/sysreg: Standardise naming for CTR_EL0 fields\n984225b8a51c BACKPORT: arm64/cache: Restrict which headers are included in __ASSEMBLY__\n291512c539b9 UPSTREAM: arm64/cpuinfo: Remove references to reserved cache type\n1baa454b7358 UPSTREAM: arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names\n162f7a4408b2 UPSTREAM: arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM\n2533256a0e8b UPSTREAM: arm64/sysreg: Guard SYS_FIELD_ macros for asm\n9279a569a08d UPSTREAM: arm64/sysreg: Directly include bitfield.h\n501dae30058b UPSTREAM: arm64/sysreg: Add SYS_FIELD_GET() helper\n1bf4f91abe97 UPSTREAM: arm64/sysreg: Introduce helpers for access to sysreg fields\neb06a93511b0 UPSTREAM: arm64: mm: Use asid feature macro for cheanup\n0c91703048ab Merge 5.15.74 into android14-5.15\nbc65b070e0e9 ANDROID: clang: update to 15.0.2\n2120596d67ea FROMLIST: ARM: NWFPE: avoid compiler-generated __aeabi_uldivmod\n6cc9804268ae Merge 5.15.73 into android14-5.15\n\nTest: treehugger\nBug: 233192153\nChange-Id: Idc4a6ebde4f4608032a86eefb919a0c8d3e3aaec\n",
  "tree_diff": [
    {
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      "old_mode": 33188,
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      "new_mode": 33188,
      "new_path": "microdroid/kernel/x86_64/System.map"
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      "new_path": "microdroid/kernel/x86_64/kernel-5.15"
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    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "microdroid/kernel/x86_64/prebuilt-info.txt",
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}