vmbase: Move CMOs under crate::arch
No functional change intended.
Test: m pvmfw_bin
Bug: 377276983
Change-Id: I203bd4ea358d845e0d7ffedc89117c5d021baf18
diff --git a/guest/pvmfw/src/entry.rs b/guest/pvmfw/src/entry.rs
index dc6b5fa..64a03cc 100644
--- a/guest/pvmfw/src/entry.rs
+++ b/guest/pvmfw/src/entry.rs
@@ -26,11 +26,12 @@
use log::LevelFilter;
use vmbase::util::RangeExt as _;
use vmbase::{
+ arch::aarch64::min_dcache_line_size,
configure_heap, console_writeln,
hyp::get_mmio_guard,
layout::{self, crosvm, UART_PAGE_ADDR},
main,
- memory::{min_dcache_line_size, MemoryTracker, MEMORY, SIZE_128KB, SIZE_4KB},
+ memory::{MemoryTracker, MEMORY, SIZE_128KB, SIZE_4KB},
power::reboot,
};
use zeroize::Zeroize;
diff --git a/libs/libvmbase/src/arch.rs b/libs/libvmbase/src/arch.rs
index ded66f2..0348800 100644
--- a/libs/libvmbase/src/arch.rs
+++ b/libs/libvmbase/src/arch.rs
@@ -35,3 +35,21 @@
}
}
}
+
+/// Flush `size` bytes of data cache by virtual address.
+#[inline]
+pub(crate) fn flush_region(start: usize, size: usize) {
+ cfg_if::cfg_if! {
+ if #[cfg(target_arch = "aarch64")] {
+ let line_size = aarch64::min_dcache_line_size();
+ let end = start + size;
+ let start = crate::util::unchecked_align_down(start, line_size);
+
+ for line in (start..end).step_by(line_size) {
+ crate::dc!("cvau", line);
+ }
+ } else {
+ compile_error!("Unsupported target_arch")
+ }
+ }
+}
diff --git a/libs/libvmbase/src/arch/aarch64.rs b/libs/libvmbase/src/arch/aarch64.rs
index d8bb2f5..5006aca 100644
--- a/libs/libvmbase/src/arch/aarch64.rs
+++ b/libs/libvmbase/src/arch/aarch64.rs
@@ -73,6 +73,23 @@
}};
}
+/// Executes a data cache operation.
+#[macro_export]
+macro_rules! dc {
+ ($option:literal, $addr:expr) => {{
+ let addr: usize = $addr;
+ #[allow(unused_unsafe)] // In case the macro is used within an unsafe block.
+ // SAFETY: Clearing cache lines shouldn't have Rust-visible side effects.
+ unsafe {
+ core::arch::asm!(
+ concat!("dc ", $option, ", {x}"),
+ x = in(reg) addr,
+ options(nomem, nostack, preserves_flags),
+ );
+ }
+ }};
+}
+
/// Invalidates cached leaf PTE entries by virtual address.
#[macro_export]
macro_rules! tlbi {
@@ -111,3 +128,16 @@
);
}
}
+
+/// Reads the number of words in the smallest cache line of all the data caches and unified caches.
+#[inline]
+pub fn min_dcache_line_size() -> usize {
+ const DMINLINE_SHIFT: usize = 16;
+ const DMINLINE_MASK: usize = 0xf;
+ let ctr_el0 = read_sysreg!("ctr_el0");
+
+ // DminLine: log2 of the number of words in the smallest cache line of all the data caches.
+ let dminline = (ctr_el0 >> DMINLINE_SHIFT) & DMINLINE_MASK;
+
+ 1 << dminline
+}
diff --git a/libs/libvmbase/src/memory.rs b/libs/libvmbase/src/memory.rs
index 89c4554..e0ea207 100644
--- a/libs/libvmbase/src/memory.rs
+++ b/libs/libvmbase/src/memory.rs
@@ -26,8 +26,8 @@
pub use shared::MemoryRange;
pub use tracker::{MemoryTracker, MEMORY};
pub use util::{
- flush, flushed_zeroize, min_dcache_line_size, page_4kb_of, PAGE_SIZE, SIZE_128KB, SIZE_16KB,
- SIZE_2MB, SIZE_4KB, SIZE_4MB, SIZE_64KB,
+ flush, flushed_zeroize, page_4kb_of, PAGE_SIZE, SIZE_128KB, SIZE_16KB, SIZE_2MB, SIZE_4KB,
+ SIZE_4MB, SIZE_64KB,
};
pub(crate) use shared::{alloc_shared, dealloc_shared};
diff --git a/libs/libvmbase/src/memory/dbm.rs b/libs/libvmbase/src/memory/dbm.rs
index 108cd5d..de43403 100644
--- a/libs/libvmbase/src/memory/dbm.rs
+++ b/libs/libvmbase/src/memory/dbm.rs
@@ -15,7 +15,7 @@
//! Hardware management of the access flag and dirty state.
use super::page_table::PageTable;
-use super::util::flush_region;
+use crate::arch::flush_region;
use crate::{dsb, isb, read_sysreg, tlbi, write_sysreg};
use aarch64_paging::paging::{Attributes, Descriptor, MemoryRegion};
diff --git a/libs/libvmbase/src/memory/util.rs b/libs/libvmbase/src/memory/util.rs
index e9f867f..cfb0fa7 100644
--- a/libs/libvmbase/src/memory/util.rs
+++ b/libs/libvmbase/src/memory/util.rs
@@ -14,9 +14,8 @@
//! Utility functions for memory management.
-use crate::read_sysreg;
+use crate::arch::flush_region;
use crate::util::unchecked_align_down;
-use core::arch::asm;
use core::ptr::NonNull;
use zeroize::Zeroize;
@@ -36,38 +35,6 @@
/// The page size in bytes assumed by vmbase - 4 KiB.
pub const PAGE_SIZE: usize = SIZE_4KB;
-/// Reads the number of words in the smallest cache line of all the data caches and unified caches.
-#[inline]
-pub fn min_dcache_line_size() -> usize {
- const DMINLINE_SHIFT: usize = 16;
- const DMINLINE_MASK: usize = 0xf;
- let ctr_el0 = read_sysreg!("ctr_el0");
-
- // DminLine: log2 of the number of words in the smallest cache line of all the data caches.
- let dminline = (ctr_el0 >> DMINLINE_SHIFT) & DMINLINE_MASK;
-
- 1 << dminline
-}
-
-/// Flush `size` bytes of data cache by virtual address.
-#[inline]
-pub(super) fn flush_region(start: usize, size: usize) {
- let line_size = min_dcache_line_size();
- let end = start + size;
- let start = unchecked_align_down(start, line_size);
-
- for line in (start..end).step_by(line_size) {
- // SAFETY: Clearing cache lines shouldn't have Rust-visible side effects.
- unsafe {
- asm!(
- "dc cvau, {x}",
- x = in(reg) line,
- options(nomem, nostack, preserves_flags),
- )
- }
- }
-}
-
/// Flushes the slice to the point of unification.
#[inline]
pub fn flush(reg: &[u8]) {