commit 713c6f3d61a2478e6b0a7ffaed05b68b188f3d6e
author Treehugger Robot <treehugger-gerrit@google.com> Wed Jul 13 07:58:14 2022 +0000
committer Gerrit Code Review <noreply-gerritcodereview@google.com> Wed Jul 13 07:58:14 2022 +0000
tree 3ddc534a66a920e696a15482e4e199a50c717774
parent 6aca0fef5dae1eef57d8d5a6487cb016cdcaf369
parent b6463c911a13728f5a5e89c61c98e6829c21165e

Merge changes Ibc5762d9,I30d6ed58,I12fa7477

* changes:
  rialto: Remove activate_kernel_pgt function
  rialto: Move PT Attributes to global constants
  rialto: Remove 'extern crate log'

rialto/Android.bp

diff --git a/rialto/Android.bp b/rialto/Android.bp
index cc71254..c2a19f3 100644
--- a/rialto/Android.bp
+++ b/rialto/Android.bp
@@ -11,6 +11,7 @@
     rustlibs: [
         "libaarch64_paging",
         "libbuddy_system_allocator",
+        "liblog_rust_nostd",
         "libvmbase",
     ],
     apex_available: ["com.android.virt"],

rialto/src/main.rs

diff --git a/rialto/src/main.rs b/rialto/src/main.rs
index a769abb..8710c49 100644
--- a/rialto/src/main.rs
+++ b/rialto/src/main.rs
@@ -21,7 +21,6 @@
 mod exceptions;
 
 extern crate alloc;
-extern crate log;
 
 use aarch64_paging::{
     idmap::IdMap,
@@ -42,6 +41,22 @@
 const PT_ROOT_LEVEL: usize = 1;
 const PT_ASID: usize = 1;
 
+const PROT_DEV: Attributes = Attributes::from_bits_truncate(
+    Attributes::DEVICE_NGNRE.bits() | Attributes::EXECUTE_NEVER.bits(),
+);
+const PROT_RX: Attributes = Attributes::from_bits_truncate(
+    Attributes::NORMAL.bits() | Attributes::NON_GLOBAL.bits() | Attributes::READ_ONLY.bits(),
+);
+const PROT_RO: Attributes = Attributes::from_bits_truncate(
+    Attributes::NORMAL.bits()
+        | Attributes::NON_GLOBAL.bits()
+        | Attributes::READ_ONLY.bits()
+        | Attributes::EXECUTE_NEVER.bits(),
+);
+const PROT_RW: Attributes = Attributes::from_bits_truncate(
+    Attributes::NORMAL.bits() | Attributes::NON_GLOBAL.bits() | Attributes::EXECUTE_NEVER.bits(),
+);
+
 #[global_allocator]
 static HEAP_ALLOCATOR: LockedHeap<32> = LockedHeap::<32>::new();
 
@@ -76,32 +91,20 @@
     let reg_rodata = unsafe { kimg_region(&rodata_begin, &rodata_end) };
     let reg_data = unsafe { kimg_region(&data_begin, &boot_stack_end) };
 
-    debug!("Preparing kernel page tables.");
+    debug!("Preparing kernel page table.");
     debug!("  dev:    {}-{}", reg_dev.start(), reg_dev.end());
     debug!("  text:   {}-{}", reg_text.start(), reg_text.end());
     debug!("  rodata: {}-{}", reg_rodata.start(), reg_rodata.end());
     debug!("  data:   {}-{}", reg_data.start(), reg_data.end());
 
-    let prot_dev = Attributes::DEVICE_NGNRE | Attributes::EXECUTE_NEVER;
-    let prot_rx = Attributes::NORMAL | Attributes::NON_GLOBAL | Attributes::READ_ONLY;
-    let prot_ro = Attributes::NORMAL
-        | Attributes::NON_GLOBAL
-        | Attributes::READ_ONLY
-        | Attributes::EXECUTE_NEVER;
-    let prot_rw = Attributes::NORMAL | Attributes::NON_GLOBAL | Attributes::EXECUTE_NEVER;
+    pgt.map_range(&reg_dev, PROT_DEV)?;
+    pgt.map_range(&reg_text, PROT_RX)?;
+    pgt.map_range(&reg_rodata, PROT_RO)?;
+    pgt.map_range(&reg_data, PROT_RW)?;
 
-    pgt.map_range(&reg_dev, prot_dev)?;
-    pgt.map_range(&reg_text, prot_rx)?;
-    pgt.map_range(&reg_rodata, prot_ro)?;
-    pgt.map_range(&reg_data, prot_rw)?;
-
-    info!("Finished preparing kernel page table.");
-    Ok(())
-}
-
-fn activate_kernel_pgt(pgt: &mut IdMap) {
     pgt.activate();
     info!("Activated kernel page table.");
+    Ok(())
 }
 
 /// Entry point for Rialto.
@@ -113,7 +116,6 @@
 
     let mut pgt = IdMap::new(PT_ASID, PT_ROOT_LEVEL);
     init_kernel_pgt(&mut pgt).unwrap();
-    activate_kernel_pgt(&mut pgt);
 }
 
 extern "C" {