vmbase: Introduce the reset_or_hang macro
Extract the logic from exceptions_panic.S as boot code might use it.
Stop zeroing registers x1-x3 as it doesn't seem to be required by PSCI.
Test: atest MicrodroidTestApp
Change-Id: I8c9eb371299152b173c8bb589dccfb6edf8d634e
diff --git a/vmbase/exceptions_panic.S b/vmbase/exceptions_panic.S
index 4a3f2db..54735b2 100644
--- a/vmbase/exceptions_panic.S
+++ b/vmbase/exceptions_panic.S
@@ -14,6 +14,8 @@
* limitations under the License.
*/
+#include <common.h>
+
/**
* The following table is intended to trap any fault resulting from the very
* first memory accesses. They assume that PSCI v0.2 is available and provides
@@ -21,80 +23,69 @@
* results in the core busy-looping.
*/
-.macro exception_panic
- mov x0, 0x84000000
- movk x0, 9
- mov x1, 0
- mov x2, 0
- mov x3, 0
- hvc 0
-0: wfi
- b 0b
-.endm
-
.section .text.vector_table_panic, "ax"
.global vector_table_panic
.balign 0x800
vector_table_panic:
sync_cur_sp0_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
irq_cur_sp0_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
fiq_cur_sp0_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
serr_cur_sp0_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
sync_cur_spx_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
irq_cur_spx_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
fiq_cur_spx_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
serr_cur_spx_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
sync_lower_64_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
irq_lower_64_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
fiq_lower_64_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
serr_lower_64_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
sync_lower_32_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
irq_lower_32_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
fiq_lower_32_panic:
- exception_panic
+ reset_or_hang
.balign 0x80
serr_lower_32_panic:
- exception_panic
+ reset_or_hang