rialto: Use PageTable from pvmfw through vmbase
Extract the file to vmbase.
Use it in Rialto to replace the existing PT manipulation cofiguration.
Bug: 282928116
Test: atest rialto_test
Change-Id: If9aaa30fb60781cebc82cf34ebe94a9a580beace
diff --git a/pvmfw/src/main.rs b/pvmfw/src/main.rs
index 9afd816..5108eb4 100644
--- a/pvmfw/src/main.rs
+++ b/pvmfw/src/main.rs
@@ -33,7 +33,6 @@
mod hvc;
mod instance;
mod memory;
-mod mmu;
mod rand;
mod virtio;
diff --git a/pvmfw/src/memory.rs b/pvmfw/src/memory.rs
index c97ed99..d4e548b 100644
--- a/pvmfw/src/memory.rs
+++ b/pvmfw/src/memory.rs
@@ -17,7 +17,6 @@
#![deny(unsafe_op_in_unsafe_fn)]
use crate::helpers::{self, page_4kb_of, RangeExt, PVMFW_PAGE_SIZE, SIZE_4MB};
-use crate::mmu::{PageTable, MMIO_LAZY_MAP_FLAG};
use aarch64_paging::idmap::IdMap;
use aarch64_paging::paging::{Attributes, Descriptor, MemoryRegion as VaRange};
use aarch64_paging::MapError;
@@ -42,7 +41,11 @@
use once_cell::race::OnceBox;
use spin::mutex::SpinMutex;
use tinyvec::ArrayVec;
-use vmbase::{dsb, isb, layout, memory::set_dbm_enabled, tlbi};
+use vmbase::{
+ dsb, isb, layout,
+ memory::{set_dbm_enabled, PageTable, MMIO_LAZY_MAP_FLAG},
+ tlbi,
+};
/// Base of the system's contiguous "main" memory.
pub const BASE_ADDR: usize = 0x8000_0000;
diff --git a/rialto/src/main.rs b/rialto/src/main.rs
index 57bed69..77999fb 100644
--- a/rialto/src/main.rs
+++ b/rialto/src/main.rs
@@ -23,16 +23,13 @@
extern crate alloc;
use crate::error::{Error, Result};
-use aarch64_paging::{
- idmap::IdMap,
- paging::{Attributes, MemoryRegion},
-};
+use aarch64_paging::idmap::IdMap;
use buddy_system_allocator::LockedHeap;
-use core::{ops::Range, slice};
+use core::slice;
use fdtpci::PciInfo;
use hyp::get_hypervisor;
use log::{debug, error, info};
-use vmbase::{layout, main, power::reboot};
+use vmbase::{layout, main, memory::PageTable, power::reboot};
const SZ_1K: usize = 1024;
const SZ_4K: usize = 4 * SZ_1K;
@@ -45,31 +42,11 @@
const PT_ROOT_LEVEL: usize = 1;
const PT_ASID: usize = 1;
-const PROT_DEV: Attributes =
- Attributes::DEVICE_NGNRE.union(Attributes::EXECUTE_NEVER).union(Attributes::VALID);
-const PROT_RX: Attributes = Attributes::NORMAL
- .union(Attributes::NON_GLOBAL)
- .union(Attributes::READ_ONLY)
- .union(Attributes::VALID);
-const PROT_RO: Attributes = Attributes::NORMAL
- .union(Attributes::NON_GLOBAL)
- .union(Attributes::READ_ONLY)
- .union(Attributes::EXECUTE_NEVER)
- .union(Attributes::VALID);
-const PROT_RW: Attributes = Attributes::NORMAL
- .union(Attributes::NON_GLOBAL)
- .union(Attributes::EXECUTE_NEVER)
- .union(Attributes::VALID);
-
#[global_allocator]
static HEAP_ALLOCATOR: LockedHeap<32> = LockedHeap::<32>::new();
static mut HEAP: [u8; SZ_64K] = [0; SZ_64K];
-fn into_memreg(r: &Range<usize>) -> MemoryRegion {
- MemoryRegion::new(r.start, r.end)
-}
-
fn init_heap() {
// SAFETY: Allocator set to otherwise unused, static memory.
unsafe {
@@ -77,28 +54,19 @@
}
}
-fn init_kernel_pgt(pgt: &mut IdMap) -> Result<()> {
+fn init_page_table() -> Result<()> {
+ let mut page_table: PageTable = IdMap::new(PT_ASID, PT_ROOT_LEVEL).into();
+
// The first 1 GiB of address space is used by crosvm for MMIO.
- let reg_dev = MemoryRegion::new(0, SZ_1G);
- let reg_text = into_memreg(&layout::text_range());
- let reg_rodata = into_memreg(&layout::rodata_range());
- let reg_scratch = into_memreg(&layout::scratch_range());
- let reg_stack = into_memreg(&layout::stack_range(40 * SZ_4K));
+ page_table.map_device(&(0..SZ_1G))?;
+ page_table.map_data(&layout::scratch_range())?;
+ page_table.map_data(&layout::stack_range(40 * SZ_4K))?;
+ page_table.map_code(&layout::text_range())?;
+ page_table.map_rodata(&layout::rodata_range())?;
- debug!("Preparing kernel page table.");
- debug!(" dev: {}-{}", reg_dev.start(), reg_dev.end());
- debug!(" text: {}-{}", reg_text.start(), reg_text.end());
- debug!(" rodata: {}-{}", reg_rodata.start(), reg_rodata.end());
- debug!(" scratch:{}-{}", reg_scratch.start(), reg_scratch.end());
- debug!(" stack: {}-{}", reg_stack.start(), reg_stack.end());
-
- pgt.map_range(®_dev, PROT_DEV)?;
- pgt.map_range(®_text, PROT_RX)?;
- pgt.map_range(®_rodata, PROT_RO)?;
- pgt.map_range(®_scratch, PROT_RW)?;
- pgt.map_range(®_stack, PROT_RW)?;
-
- pgt.activate();
+ // SAFETY: It is safe to activate the page table by setting `TTBR0_EL1` to point to
+ // it as this is the first time we activate the page table.
+ unsafe { page_table.activate() }
info!("Activated kernel page table.");
Ok(())
}
@@ -126,8 +94,7 @@
let pci_info = PciInfo::from_fdt(fdt)?;
debug!("PCI: {:#x?}", pci_info);
- let mut pgt = IdMap::new(PT_ASID, PT_ROOT_LEVEL);
- init_kernel_pgt(&mut pgt)?;
+ init_page_table()?;
Ok(())
}
diff --git a/vmbase/Android.bp b/vmbase/Android.bp
index e55dbb0..9b246c0 100644
--- a/vmbase/Android.bp
+++ b/vmbase/Android.bp
@@ -63,6 +63,7 @@
crate_name: "vmbase",
srcs: ["src/lib.rs"],
rustlibs: [
+ "libaarch64_paging",
"liblog_rust_nostd",
"libsmccc",
"libspin_nostd",
diff --git a/vmbase/src/memory/mod.rs b/vmbase/src/memory/mod.rs
index c4990f2..149fd18 100644
--- a/vmbase/src/memory/mod.rs
+++ b/vmbase/src/memory/mod.rs
@@ -15,5 +15,7 @@
//! Memory management.
mod dbm;
+mod page_table;
pub use dbm::set_dbm_enabled;
+pub use page_table::{PageTable, MMIO_LAZY_MAP_FLAG};
diff --git a/pvmfw/src/mmu.rs b/vmbase/src/memory/page_table.rs
similarity index 100%
rename from pvmfw/src/mmu.rs
rename to vmbase/src/memory/page_table.rs