Serial devices follows the legacy order
crosvm uses the same legacy order (3f8, 2f8, 3e8, 2e8) across x86 and
arm64. crosvm once tried to change that for non-x86 architecture
(because it doesn't have to), but that didn't land because there were
existing use case where the legacy order is expected.
This change makes sure that the serial device order is not changed by
the rewrite of the device tree by pvmfw.
Bug: 330659544
Test: run microdroid in pvm and check the kernel log
Change-Id: I3cfecc882148d0d1edd1a699123a0d26cee9ce95
diff --git a/pvmfw/platform.dts b/pvmfw/platform.dts
index 68acf13..99ecf8f 100644
--- a/pvmfw/platform.dts
+++ b/pvmfw/platform.dts
@@ -308,11 +308,11 @@
GIC_PPI 0xa IRQ_TYPE_LEVEL_LOW>;
};
- uart@2e8 {
+ uart@3f8 {
compatible = "ns16550a";
- reg = <0x00 0x2e8 0x00 0x8>;
+ reg = <0x00 0x3f8 0x00 0x8>;
clock-frequency = <0x1c2000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
uart@2f8 {
@@ -329,11 +329,11 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
- uart@3f8 {
+ uart@2e8 {
compatible = "ns16550a";
- reg = <0x00 0x3f8 0x00 0x8>;
+ reg = <0x00 0x2e8 0x00 0x8>;
clock-frequency = <0x1c2000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
};
psci {