| Bram Moolenaar | 92dff18 | 2014-02-11 19:15:50 +0100 | [diff] [blame] | 1 | " Vim syntax file |
| 2 | " Language: SystemVerilog |
| 3 | " Maintainer: kocha <kocha.lsifrontend@gmail.com> |
| 4 | " Last Change: 12-Aug-2013. |
| 5 | |
| 6 | " For version 5.x: Clear all syntax items |
| 7 | " For version 6.x: Quit when a syntax file was already loaded |
| 8 | if version < 600 |
| 9 | syntax clear |
| 10 | elseif exists("b:current_syntax") |
| 11 | finish |
| 12 | endif |
| 13 | |
| 14 | " Read in Verilog syntax files |
| 15 | if version < 600 |
| 16 | so <sfile>:p:h/verilog.vim |
| 17 | else |
| 18 | runtime! syntax/verilog.vim |
| 19 | unlet b:current_syntax |
| 20 | endif |
| 21 | |
| 22 | " IEEE1800-2005 |
| 23 | syn keyword systemverilogStatement always_comb always_ff always_latch |
| 24 | syn keyword systemverilogStatement class endclass new |
| 25 | syn keyword systemverilogStatement virtual local const protected |
| 26 | syn keyword systemverilogStatement package endpackage |
| 27 | syn keyword systemverilogStatement rand randc constraint randomize |
| 28 | syn keyword systemverilogStatement with inside dist |
| 29 | syn keyword systemverilogStatement sequence endsequence randsequence |
| 30 | syn keyword systemverilogStatement srandom |
| 31 | syn keyword systemverilogStatement logic bit byte |
| 32 | syn keyword systemverilogStatement int longint shortint |
| 33 | syn keyword systemverilogStatement struct packed |
| 34 | syn keyword systemverilogStatement final |
| 35 | syn keyword systemverilogStatement import export |
| 36 | syn keyword systemverilogStatement context pure |
| 37 | syn keyword systemverilogStatement void shortreal chandle string |
| 38 | syn keyword systemverilogStatement clocking endclocking iff |
| 39 | syn keyword systemverilogStatement interface endinterface modport |
| 40 | syn keyword systemverilogStatement cover covergroup coverpoint endgroup |
| 41 | syn keyword systemverilogStatement property endproperty |
| 42 | syn keyword systemverilogStatement program endprogram |
| 43 | syn keyword systemverilogStatement bins binsof illegal_bins ignore_bins |
| 44 | syn keyword systemverilogStatement alias matches solve static assert |
| 45 | syn keyword systemverilogStatement assume super before expect bind |
| 46 | syn keyword systemverilogStatement extends null tagged extern this |
| 47 | syn keyword systemverilogStatement first_match throughout timeprecision |
| 48 | syn keyword systemverilogStatement timeunit type union |
| 49 | syn keyword systemverilogStatement uwire var cross ref wait_order intersect |
| 50 | syn keyword systemverilogStatement wildcard within |
| 51 | |
| 52 | syn keyword systemverilogTypeDef typedef enum |
| 53 | |
| 54 | syn keyword systemverilogConditional randcase |
| 55 | syn keyword systemverilogConditional unique priority |
| 56 | |
| 57 | syn keyword systemverilogRepeat return break continue |
| 58 | syn keyword systemverilogRepeat do foreach |
| 59 | |
| 60 | syn keyword systemverilogLabel join_any join_none forkjoin |
| 61 | |
| 62 | " IEEE1800-2009 add |
| 63 | syn keyword systemverilogStatement checker endchecker |
| 64 | syn keyword systemverilogStatement accept_on reject_on |
| 65 | syn keyword systemverilogStatement sync_accept_on sync_reject_on |
| 66 | syn keyword systemverilogStatement eventually nexttime until until_with |
| 67 | syn keyword systemverilogStatement s_always s_eventually s_nexttime s_until s_until_with |
| 68 | syn keyword systemverilogStatement let untyped |
| 69 | syn keyword systemverilogStatement strong weak |
| 70 | syn keyword systemverilogStatement restrict global implies |
| 71 | |
| 72 | syn keyword systemverilogConditional unique0 |
| 73 | |
| 74 | " IEEE1800-2012 add |
| 75 | syn keyword systemverilogStatement implements |
| 76 | syn keyword systemverilogStatement interconnect soft nettype |
| 77 | |
| 78 | " Define the default highlighting. |
| 79 | if version >= 508 || !exists("did_systemverilog_syn_inits") |
| 80 | if version < 508 |
| 81 | let did_systemverilog_syn_inits = 1 |
| 82 | command -nargs=+ HiLink hi link <args> |
| 83 | else |
| 84 | command -nargs=+ HiLink hi def link <args> |
| 85 | endif |
| 86 | |
| 87 | " The default highlighting. |
| 88 | HiLink systemverilogStatement Statement |
| 89 | HiLink systemverilogTypeDef TypeDef |
| 90 | HiLink systemverilogConditional Conditional |
| 91 | HiLink systemverilogRepeat Repeat |
| 92 | HiLink systemverilogLabel Label |
| 93 | HiLink systemverilogGlobal Define |
| 94 | HiLink systemverilogNumber Number |
| 95 | |
| 96 | delcommand HiLink |
| 97 | endif |
| 98 | |
| 99 | let b:current_syntax = "systemverilog" |
| 100 | |
| 101 | " vim: ts=8 |