commit f1568eca24d30d4f308e987657c53cd48d97d8fa
author Bram Moolenaar <Bram@vim.org> Wed Dec 14 21:17:39 2011 +0100
committer Bram Moolenaar <Bram@vim.org> Wed Dec 14 21:17:39 2011 +0100
tree 900c802d8096eca43c957c0b3c16cc36cec32e7b
parent f788a0610309ed9787b4e48216c7d7d4446744c5

Update runtime files.

runtime/indent/verilog.vim

diff --git a/runtime/indent/verilog.vim b/runtime/indent/verilog.vim
index 74c8c5f..ecca462 100644
--- a/runtime/indent/verilog.vim
+++ b/runtime/indent/verilog.vim
@@ -1,6 +1,6 @@
 " Language:     Verilog HDL
 " Maintainer:	Chih-Tsun Huang <cthuang@larc.ee.nthu.edu.tw>
-" Last Change:	Wed Oct 31 16:13:11 CST 2001
+" Last Change:	2011 Dec 10 by Thilo Six
 " URL:		http://larc.ee.nthu.edu.tw/~cthuang/vim/indent/verilog.vim
 "
 " Credits:
@@ -30,7 +30,8 @@
   finish
 endif
 
-set cpo-=C
+let s:cpo_save = &cpo
+set cpo&vim
 
 function GetVerilogIndent()
 
@@ -216,4 +217,7 @@
   return ind
 endfunction
 
+let &cpo = s:cpo_save
+unlet s:cpo_save
+
 " vim:sw=2