diff --git a/runtime/autoload/dist/ft.vim b/runtime/autoload/dist/ft.vim
index 5d2053d..4e0906d 100644
--- a/runtime/autoload/dist/ft.vim
+++ b/runtime/autoload/dist/ft.vim
@@ -1106,5 +1106,40 @@
   endif
 enddef
 
+# Set the filetype of a *.v file to Verilog, V or Cog based on the first 200
+# lines.
+export def FTv()
+  if did_filetype()
+    # ":setf" will do nothing, bail out early
+    return
+  endif
+
+  for line in getline(1, 200)
+    if line[0] =~ '^\s*/'
+      # skip comment line
+      continue
+    endif
+
+    # Verilog: line ends with ';' followed by an optional variable number of
+    # spaces and an optional start of a comment.
+    # Example: " b <= a + 1; // Add 1".
+    if line =~ ';\(\s*\)\?\(/.*\)\?$'
+      setf verilog
+      return
+    endif
+
+    # Coq: line ends with a '.' followed by an optional variable number of
+    # spaces and an optional start of a comment.
+    # Example: "Definition x := 10. (*".
+    if line =~ '\.\(\s*\)\?\((\*.*\)\?$'
+      setf coq
+      return
+    endif
+  endfor
+
+  # No line matched, fall back to "v".
+  setf v
+enddef
+
 # Uncomment this line to check for compilation errors early
 # defcompile
diff --git a/runtime/filetype.vim b/runtime/filetype.vim
index 50187f6..538ddd8 100644
--- a/runtime/filetype.vim
+++ b/runtime/filetype.vim
@@ -2303,8 +2303,8 @@
 " Vagrant (uses Ruby syntax)
 au BufNewFile,BufRead Vagrantfile		setf ruby
 
-" Verilog HDL
-au BufNewFile,BufRead *.v			setf verilog
+" Verilog HDL, V or Coq
+au BufNewFile,BufRead *.v			call dist#ft#FTv()
 
 " Verilog-AMS HDL
 au BufNewFile,BufRead *.va,*.vams		setf verilogams
diff --git a/src/testdir/test_filetype.vim b/src/testdir/test_filetype.vim
index f399f1b..8518770 100644
--- a/src/testdir/test_filetype.vim
+++ b/src/testdir/test_filetype.vim
@@ -646,7 +646,6 @@
     \ 'vdmrt': ['file.vdmrt'],
     \ 'vdmsl': ['file.vdm', 'file.vdmsl'],
     \ 'vera': ['file.vr', 'file.vri', 'file.vrh'],
-    \ 'verilog': ['file.v'],
     \ 'verilogams': ['file.va', 'file.vams'],
     \ 'vgrindefs': ['vgrindefs'],
     \ 'vhdl': ['file.hdl', 'file.vhd', 'file.vhdl', 'file.vbe', 'file.vst', 'file.vhdl_123', 'file.vho', 'some.vhdl_1', 'some.vhdl_1-file'],
@@ -1771,6 +1770,27 @@
   filetype off
 endfunc
 
+func Test_v_file()
+  filetype on
+
+  call writefile(['module tb; // Looks like a Verilog'], 'Xfile.v', 'D')
+  split Xfile.v
+  call assert_equal('verilog', &filetype)
+  bwipe!
+
+  call writefile(['module main'], 'Xfile.v')
+  split Xfile.v
+  call assert_equal('v', &filetype)
+  bwipe!
+
+  call writefile(['Definition x := 10.  (*'], 'Xfile.v')
+  split Xfile.v
+  call assert_equal('coq', &filetype)
+  bwipe!
+
+  filetype off
+endfunc
+
 func Test_xpm_file()
   filetype on
 
diff --git a/src/version.c b/src/version.c
index c94a503..0df4436 100644
--- a/src/version.c
+++ b/src/version.c
@@ -696,6 +696,8 @@
 static int included_patches[] =
 {   /* Add new patch number below this line */
 /**/
+    1478,
+/**/
     1477,
 /**/
     1476,