diff --git a/platformnv.cpp b/platformnv.cpp
index 9ea1467..ca65e72 100644
--- a/platformnv.cpp
+++ b/platformnv.cpp
@@ -275,7 +275,7 @@
   return 0;
 }
 
-bool PlanStageNvLimits::CheckLayer(DrmHwcLayer *layer) {
+bool PlanStageNvLimits::CheckLayer(size_t zorder, DrmHwcLayer *layer) {
     auto src_w = layer->source_crop.width();
     auto src_h = layer->source_crop.height();
     auto dst_w = layer->display_frame.width();
@@ -284,6 +284,17 @@
     int v_limit;
 
     switch (layer->buffer->format) {
+      case DRM_FORMAT_ARGB8888:
+      case DRM_FORMAT_ABGR8888:
+      case DRM_FORMAT_XBGR8888:
+        // tegra driver assumes any layer with alpha channel has premult
+        // blending, avoid handling it this is not the case. This is not an
+        // issue for bottom-most layer since there's nothing to blend with
+        if (zorder > 0 && layer->blending != DrmHwcBlending::kPreMult)
+          return false;
+
+        v_limit = 2;
+        break;
       case DRM_FORMAT_YVU420:
       case DRM_FORMAT_BGR565:
         v_limit = 4;
@@ -312,7 +323,7 @@
 
   for (auto i = layers.begin(); i != layers.end();) {
     // Skip layer if supported
-    if (CheckLayer(i->second)) {
+    if (CheckLayer(i->first, i->second)) {
       i++;
       continue;
     }
diff --git a/platformnv.h b/platformnv.h
index df2a242..e379ea9 100644
--- a/platformnv.h
+++ b/platformnv.h
@@ -82,7 +82,7 @@
                       std::map<size_t, DrmHwcLayer *> &layers, DrmCrtc *crtc,
                       std::vector<DrmPlane *> *planes);
  protected:
-  bool CheckLayer(DrmHwcLayer *layer);
+  bool CheckLayer(size_t zorder, DrmHwcLayer *layer);
 };
 }