riscv64: disable a weird option.
By default clang assumes that on riscv64 jumps are really expensive.
That's probably not true for the kind of SoCs we're dealing with, but
more importantly (see the bug) it causes clang to do loads from the
right hand side of a `&&` before the left hand side has been evaluated.
This found one latent bug in libcore, and it doesn't seem like the best
use of anyone's time to have to chase similar issues if they're going
to be similarly latent for riscv64 when we get clang's default fixed.
Bug: https://github.com/google/android-riscv64/issues/124
Test: treehugger
Change-Id: I640f1b43ea3d2452366ab86e97a9189fa9f5326c
diff --git a/cc/config/riscv64_device.go b/cc/config/riscv64_device.go
index e820260..0964015 100644
--- a/cc/config/riscv64_device.go
+++ b/cc/config/riscv64_device.go
@@ -39,6 +39,9 @@
// Equivalent to "-munaligned-access", but our clang doesn't have that yet.
"-Xclang -target-feature -Xclang +unaligned-scalar-mem",
"-Xclang -target-feature -Xclang +unaligned-vector-mem",
+ // We should change the default for this in clang, but for now...
+ // (https://github.com/google/android-riscv64/issues/124)
+ "-mllvm -jump-is-expensive=false",
}
riscv64Lldflags = append(riscv64Ldflags,