commit 357778de34c7e8aa31a0baec1ab45fcf31dde234
author Mingwei Shi <mingwei.shi@intel.com> Mon Mar 09 19:44:49 2015 +0800
committer Mingwei Shi <mingwei.shi@intel.com> Thu Mar 12 22:45:27 2015 +0800
tree 4cddcee4a70ca7568d28764e846e1b926001f704
parent 46ba5456ad33e0674929eefff0753e21301e6eba

Update x86_64 minimal ISA instruction set

Change-Id: I3ca7f8a0799e6aef09ab1dfb719d218c7338ebf8
Signed-off-by: Mingwei Shi <mingwei.shi@intel.com>

core/combo/TARGET_linux-x86_64.mk

diff --git a/core/combo/TARGET_linux-x86_64.mk b/core/combo/TARGET_linux-x86_64.mk
index 046a42b..303ea82 100644
--- a/core/combo/TARGET_linux-x86_64.mk
+++ b/core/combo/TARGET_linux-x86_64.mk
@@ -117,6 +117,9 @@
 ifeq ($(ARCH_X86_HAVE_SSE4_2),true)
     TARGET_GLOBAL_CFLAGS += -msse4.2
 endif
+ifeq ($(ARCH_X86_HAVE_POPCNT),true)
+    TARGET_GLOBAL_CFLAGS += -mpopcnt
+endif
 ifeq ($(ARCH_X86_HAVE_AVX),true)
     TARGET_GLOBAL_CFLAGS += -mavx
 endif

core/combo/arch/x86_64/x86_64.mk

diff --git a/core/combo/arch/x86_64/x86_64.mk b/core/combo/arch/x86_64/x86_64.mk
index 9d2b620..08dd9cd 100755
--- a/core/combo/arch/x86_64/x86_64.mk
+++ b/core/combo/arch/x86_64/x86_64.mk
@@ -8,6 +8,9 @@
 ARCH_X86_HAVE_SSSE3 := true
 ARCH_X86_HAVE_MOVBE := false # Only supported on Atom.
 ARCH_X86_HAVE_POPCNT := true
+ARCH_X86_HAVE_SSE4 := true
+ARCH_X86_HAVE_SSE4_1 := true
+ARCH_X86_HAVE_SSE4_2 := true
 
 
 # CFLAGS for this arch