add silvermont x86 architecture
This is used for Baytrail targets.
Change-Id: I5a2fa6dbb8217a326ee09f5ea434885718ab3f0c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
Signed-off-by: Fengwei Yin <fengwei.yin@intel.com>
diff --git a/core/combo/arch/x86/silvermont.mk b/core/combo/arch/x86/silvermont.mk
new file mode 100644
index 0000000..3a8718d
--- /dev/null
+++ b/core/combo/arch/x86/silvermont.mk
@@ -0,0 +1,20 @@
+# This file contains feature macro definitions specific to the
+# silvermont arch variant.
+#
+# See build/core/combo/arch/x86/x86-atom.mk for differences.
+#
+
+ARCH_X86_HAVE_SSSE3 := true
+ARCH_X86_HAVE_SSE4 := true
+ARCH_X86_HAVE_SSE4_1 := true
+ARCH_X86_HAVE_SSE4_2 := true
+ARCH_X86_HAVE_AES_NI := true
+ARCH_X86_HAVE_POPCNT := true
+ARCH_X86_HAVE_MOVBE := true
+
+# CFLAGS for this arch
+arch_variant_cflags := \
+ -march=slm \
+ -mstackrealign \
+ -mfpmath=sse \
+
diff --git a/core/combo/arch/x86_64/silvermont.mk b/core/combo/arch/x86_64/silvermont.mk
new file mode 100644
index 0000000..6c953a3
--- /dev/null
+++ b/core/combo/arch/x86_64/silvermont.mk
@@ -0,0 +1,17 @@
+# This file contains feature macro definitions specific to the
+# silvermont arch variant.
+#
+# See build/core/combo/arch/x86/x86-atom.mk for differences.
+#
+
+ARCH_X86_HAVE_SSSE3 := true
+ARCH_X86_HAVE_SSE4 := true
+ARCH_X86_HAVE_SSE4_1 := true
+ARCH_X86_HAVE_SSE4_2 := true
+ARCH_X86_HAVE_AES_NI := true
+ARCH_X86_HAVE_POPCNT := true
+ARCH_X86_HAVE_MOVBE := true
+
+# CFLAGS for this arch
+arch_variant_cflags := \
+ -march=slm \