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Christopher Ferris6a9755d2017-01-13 14:09:31 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef MLX5_ABI_USER_H
20#define MLX5_ABI_USER_H
21#include <linux/types.h>
Christopher Ferris525ce912017-07-26 13:12:53 -070022#include <linux/if_ether.h>
Christopher Ferris9ce28842018-10-25 12:11:39 -070023#include <rdma/ib_user_ioctl_verbs.h>
Christopher Ferris6a9755d2017-01-13 14:09:31 -080024enum {
Christopher Ferris6a9755d2017-01-13 14:09:31 -080025 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
26 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
Christopher Ferris934ec942018-01-31 15:29:16 -080027 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
Christopher Ferris76a1d452018-06-27 14:12:29 -070028 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
29 MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
30 MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
Christopher Ferris86a48372019-01-10 14:14:59 -080031 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
32 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
33 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080034};
35enum {
Christopher Ferris6a9755d2017-01-13 14:09:31 -080036 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
37};
38enum {
39 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080040};
41#define MLX5_IB_UVERBS_ABI_VERSION 1
42struct mlx5_ib_alloc_ucontext_req {
Christopher Ferris525ce912017-07-26 13:12:53 -070043 __u32 total_num_bfregs;
44 __u32 num_low_latency_bfregs;
45};
46enum mlx5_lib_caps {
47 MLX5_LIB_CAP_4K_UAR = (__u64) 1 << 0,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080048};
Christopher Ferris9ce28842018-10-25 12:11:39 -070049enum mlx5_ib_alloc_uctx_v2_flags {
50 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0,
51};
Christopher Ferris6a9755d2017-01-13 14:09:31 -080052struct mlx5_ib_alloc_ucontext_req_v2 {
Christopher Ferris525ce912017-07-26 13:12:53 -070053 __u32 total_num_bfregs;
54 __u32 num_low_latency_bfregs;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080055 __u32 flags;
56 __u32 comp_mask;
57 __u8 max_cqe_version;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080058 __u8 reserved0;
59 __u16 reserved1;
60 __u32 reserved2;
Christopher Ferris76a1d452018-06-27 14:12:29 -070061 __aligned_u64 lib_caps;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080062};
Christopher Ferris6a9755d2017-01-13 14:09:31 -080063enum mlx5_ib_alloc_ucontext_resp_mask {
64 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
Christopher Ferris9ce28842018-10-25 12:11:39 -070065 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080066};
67enum mlx5_user_cmds_supp_uhw {
Christopher Ferris6a9755d2017-01-13 14:09:31 -080068 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080069 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080070};
Christopher Ferris525ce912017-07-26 13:12:53 -070071enum mlx5_user_inline_mode {
72 MLX5_USER_INLINE_MODE_NA,
73 MLX5_USER_INLINE_MODE_NONE,
74 MLX5_USER_INLINE_MODE_L2,
75 MLX5_USER_INLINE_MODE_IP,
76 MLX5_USER_INLINE_MODE_TCP_UDP,
77};
Christopher Ferris76a1d452018-06-27 14:12:29 -070078enum {
79 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
80 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
81 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
82 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
83 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
84};
Christopher Ferris6a9755d2017-01-13 14:09:31 -080085struct mlx5_ib_alloc_ucontext_resp {
Christopher Ferris48af7cb2017-02-21 12:35:09 -080086 __u32 qp_tab_size;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080087 __u32 bf_reg_size;
Christopher Ferris525ce912017-07-26 13:12:53 -070088 __u32 tot_bfregs;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080089 __u32 cache_line_size;
Christopher Ferris48af7cb2017-02-21 12:35:09 -080090 __u16 max_sq_desc_sz;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080091 __u16 max_rq_desc_sz;
92 __u32 max_send_wqebb;
93 __u32 max_recv_wr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -080094 __u32 max_srq_recv_wr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080095 __u16 num_ports;
Christopher Ferris76a1d452018-06-27 14:12:29 -070096 __u16 flow_action_flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080097 __u32 comp_mask;
Christopher Ferris48af7cb2017-02-21 12:35:09 -080098 __u32 response_length;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080099 __u8 cqe_version;
100 __u8 cmds_supp_uhw;
Christopher Ferris525ce912017-07-26 13:12:53 -0700101 __u8 eth_min_inline;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700102 __u8 clock_info_versions;
103 __aligned_u64 hca_core_clock_offset;
Christopher Ferris525ce912017-07-26 13:12:53 -0700104 __u32 log_uar_size;
105 __u32 num_uars_per_page;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700106 __u32 num_dyn_bfregs;
Christopher Ferris9ce28842018-10-25 12:11:39 -0700107 __u32 dump_fill_mkey;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800108};
109struct mlx5_ib_alloc_pd_resp {
110 __u32 pdn;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800111};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800112struct mlx5_ib_tso_caps {
113 __u32 max_tso;
114 __u32 supported_qpts;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800115};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800116struct mlx5_ib_rss_caps {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700117 __aligned_u64 rx_hash_fields_mask;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800118 __u8 rx_hash_function;
119 __u8 reserved[7];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800120};
121enum mlx5_ib_cqe_comp_res_format {
122 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800123 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
Christopher Ferris9ce28842018-10-25 12:11:39 -0700124 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800125};
126struct mlx5_ib_cqe_comp_caps {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800127 __u32 max_num;
128 __u32 supported_format;
129};
Christopher Ferris76a1d452018-06-27 14:12:29 -0700130enum mlx5_ib_packet_pacing_cap_flags {
131 MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
132};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800133struct mlx5_packet_pacing_caps {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800134 __u32 qp_rate_limit_min;
135 __u32 qp_rate_limit_max;
136 __u32 supported_qpts;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700137 __u8 cap_flags;
138 __u8 reserved[3];
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800139};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800140enum mlx5_ib_mpw_caps {
141 MPW_RESERVED = 1 << 0,
142 MLX5_IB_ALLOW_MPW = 1 << 1,
143 MLX5_IB_SUPPORT_EMPW = 1 << 2,
144};
145enum mlx5_ib_sw_parsing_offloads {
146 MLX5_IB_SW_PARSING = 1 << 0,
147 MLX5_IB_SW_PARSING_CSUM = 1 << 1,
148 MLX5_IB_SW_PARSING_LSO = 1 << 2,
149};
150struct mlx5_ib_sw_parsing_caps {
151 __u32 sw_parsing_offloads;
152 __u32 supported_qpts;
153};
Christopher Ferris934ec942018-01-31 15:29:16 -0800154struct mlx5_ib_striding_rq_caps {
155 __u32 min_single_stride_log_num_of_bytes;
156 __u32 max_single_stride_log_num_of_bytes;
157 __u32 min_single_wqe_log_num_of_strides;
158 __u32 max_single_wqe_log_num_of_strides;
159 __u32 supported_qpts;
160 __u32 reserved;
161};
162enum mlx5_ib_query_dev_resp_flags {
163 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
164 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
165};
166enum mlx5_ib_tunnel_offloads {
167 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
168 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
Christopher Ferris9ce28842018-10-25 12:11:39 -0700169 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
170 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
171 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
Christopher Ferris934ec942018-01-31 15:29:16 -0800172};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800173struct mlx5_ib_query_device_resp {
174 __u32 comp_mask;
175 __u32 response_length;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800176 struct mlx5_ib_tso_caps tso_caps;
177 struct mlx5_ib_rss_caps rss_caps;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800178 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
179 struct mlx5_packet_pacing_caps packet_pacing_caps;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800180 __u32 mlx5_ib_support_multi_pkt_send_wqes;
Christopher Ferris934ec942018-01-31 15:29:16 -0800181 __u32 flags;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800182 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
Christopher Ferris934ec942018-01-31 15:29:16 -0800183 struct mlx5_ib_striding_rq_caps striding_rq_caps;
184 __u32 tunnel_offloads_caps;
185 __u32 reserved;
186};
187enum mlx5_ib_create_cq_flags {
188 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800189};
190struct mlx5_ib_create_cq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700191 __aligned_u64 buf_addr;
192 __aligned_u64 db_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800193 __u32 cqe_size;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800194 __u8 cqe_comp_en;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800195 __u8 cqe_comp_res_format;
Christopher Ferris934ec942018-01-31 15:29:16 -0800196 __u16 flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800197};
198struct mlx5_ib_create_cq_resp {
199 __u32 cqn;
200 __u32 reserved;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800201};
202struct mlx5_ib_resize_cq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700203 __aligned_u64 buf_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800204 __u16 cqe_size;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800205 __u16 reserved0;
206 __u32 reserved1;
207};
208struct mlx5_ib_create_srq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700209 __aligned_u64 buf_addr;
210 __aligned_u64 db_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800211 __u32 flags;
212 __u32 reserved0;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800213 __u32 uidx;
214 __u32 reserved1;
215};
216struct mlx5_ib_create_srq_resp {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800217 __u32 srqn;
218 __u32 reserved;
219};
220struct mlx5_ib_create_qp {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700221 __aligned_u64 buf_addr;
222 __aligned_u64 db_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800223 __u32 sq_wqe_count;
224 __u32 rq_wqe_count;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800225 __u32 rq_wqe_shift;
226 __u32 flags;
227 __u32 uidx;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700228 __u32 bfreg_index;
229 union {
230 __aligned_u64 sq_buf_addr;
231 __aligned_u64 access_key;
232 };
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800233};
234enum mlx5_rx_hash_function_flags {
235 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800236};
237enum mlx5_rx_hash_fields {
238 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
239 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800240 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
241 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
242 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
243 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800244 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
Christopher Ferris934ec942018-01-31 15:29:16 -0800245 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
Christopher Ferris76a1d452018-06-27 14:12:29 -0700246 MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
247 MLX5_RX_HASH_INNER = (1UL << 31),
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800248};
249struct mlx5_ib_create_qp_rss {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700250 __aligned_u64 rx_hash_fields_mask;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800251 __u8 rx_hash_function;
252 __u8 rx_key_len;
253 __u8 reserved[6];
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800254 __u8 rx_hash_key[128];
255 __u32 comp_mask;
Christopher Ferris934ec942018-01-31 15:29:16 -0800256 __u32 flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800257};
Christopher Ferris86a48372019-01-10 14:14:59 -0800258enum mlx5_ib_create_qp_resp_mask {
259 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
260 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
261 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2,
262 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3,
263};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800264struct mlx5_ib_create_qp_resp {
Christopher Ferris525ce912017-07-26 13:12:53 -0700265 __u32 bfreg_index;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700266 __u32 reserved;
Christopher Ferris86a48372019-01-10 14:14:59 -0800267 __u32 comp_mask;
268 __u32 tirn;
269 __u32 tisn;
270 __u32 rqn;
271 __u32 sqn;
272 __u32 reserved1;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800273};
274struct mlx5_ib_alloc_mw {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800275 __u32 comp_mask;
276 __u8 num_klms;
277 __u8 reserved1;
278 __u16 reserved2;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800279};
Christopher Ferris934ec942018-01-31 15:29:16 -0800280enum mlx5_ib_create_wq_mask {
281 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
282};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800283struct mlx5_ib_create_wq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700284 __aligned_u64 buf_addr;
285 __aligned_u64 db_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800286 __u32 rq_wqe_count;
287 __u32 rq_wqe_shift;
288 __u32 user_index;
289 __u32 flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800290 __u32 comp_mask;
Christopher Ferris934ec942018-01-31 15:29:16 -0800291 __u32 single_stride_log_num_of_bytes;
292 __u32 single_wqe_log_num_of_strides;
293 __u32 two_byte_shift_en;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800294};
295struct mlx5_ib_create_ah_resp {
296 __u32 response_length;
297 __u8 dmac[ETH_ALEN];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800298 __u8 reserved[6];
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800299};
Christopher Ferris76a1d452018-06-27 14:12:29 -0700300struct mlx5_ib_burst_info {
301 __u32 max_burst_sz;
302 __u16 typical_pkt_sz;
303 __u16 reserved;
304};
305struct mlx5_ib_modify_qp {
306 __u32 comp_mask;
307 struct mlx5_ib_burst_info burst_info;
308 __u32 reserved;
309};
310struct mlx5_ib_modify_qp_resp {
311 __u32 response_length;
312 __u32 dctn;
313};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800314struct mlx5_ib_create_wq_resp {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800315 __u32 response_length;
316 __u32 reserved;
317};
318struct mlx5_ib_create_rwq_ind_tbl_resp {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800319 __u32 response_length;
320 __u32 reserved;
321};
322struct mlx5_ib_modify_wq {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800323 __u32 comp_mask;
324 __u32 reserved;
325};
Christopher Ferris76a1d452018-06-27 14:12:29 -0700326struct mlx5_ib_clock_info {
327 __u32 sign;
328 __u32 resv;
329 __aligned_u64 nsec;
330 __aligned_u64 cycles;
331 __aligned_u64 frac;
332 __u32 mult;
333 __u32 shift;
334 __aligned_u64 mask;
335 __aligned_u64 overflow_period;
336};
337enum mlx5_ib_mmap_cmd {
338 MLX5_IB_MMAP_REGULAR_PAGE = 0,
339 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
340 MLX5_IB_MMAP_WC_PAGE = 2,
341 MLX5_IB_MMAP_NC_PAGE = 3,
342 MLX5_IB_MMAP_CORE_CLOCK = 5,
343 MLX5_IB_MMAP_ALLOC_WC = 6,
344 MLX5_IB_MMAP_CLOCK_INFO = 7,
345 MLX5_IB_MMAP_DEVICE_MEM = 8,
346};
347enum {
348 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
349};
350enum {
351 MLX5_IB_CLOCK_INFO_V1 = 0,
352};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700353struct mlx5_ib_flow_counters_desc {
354 __u32 description;
355 __u32 index;
356};
357struct mlx5_ib_flow_counters_data {
358 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
359 __u32 ncounters;
360 __u32 reserved;
361};
362struct mlx5_ib_create_flow {
363 __u32 ncounters_data;
364 __u32 reserved;
365 struct mlx5_ib_flow_counters_data data[];
366};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800367#endif