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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __SOUND_HDSPM_H
20#define __SOUND_HDSPM_H
Christopher Ferris05d08e92016-02-04 13:16:38 -080021#include <linux/types.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070022#define HDSPM_MAX_CHANNELS 64
Christopher Ferris05d08e92016-02-04 13:16:38 -080023enum hdspm_io_type {
Tao Baod7db5942015-01-28 10:07:51 -080024 MADI,
25 MADIface,
26 AIO,
Christopher Ferris05d08e92016-02-04 13:16:38 -080027 AES32,
Tao Baod7db5942015-01-28 10:07:51 -080028 RayDAT
Ben Cheng655a7c02013-10-16 16:09:24 -070029};
30enum hdspm_speed {
Christopher Ferris05d08e92016-02-04 13:16:38 -080031 ss,
Tao Baod7db5942015-01-28 10:07:51 -080032 ds,
33 qs
Ben Cheng655a7c02013-10-16 16:09:24 -070034};
35struct hdspm_peak_rms {
Christopher Ferris05d08e92016-02-04 13:16:38 -080036 __u32 input_peaks[64];
37 __u32 playback_peaks[64];
38 __u32 output_peaks[64];
Christopher Ferris05d08e92016-02-04 13:16:38 -080039 __u64 input_rms[64];
40 __u64 playback_rms[64];
41 __u64 output_rms[64];
42 __u8 speed;
Tao Baod7db5942015-01-28 10:07:51 -080043 int status2;
Ben Cheng655a7c02013-10-16 16:09:24 -070044};
Tao Baod7db5942015-01-28 10:07:51 -080045#define SNDRV_HDSPM_IOCTL_GET_PEAK_RMS _IOR('H', 0x42, struct hdspm_peak_rms)
Ben Cheng655a7c02013-10-16 16:09:24 -070046struct hdspm_config {
Christopher Ferris05d08e92016-02-04 13:16:38 -080047 unsigned char pref_sync_ref;
Tao Baod7db5942015-01-28 10:07:51 -080048 unsigned char wordclock_sync_check;
49 unsigned char madi_sync_check;
50 unsigned int system_sample_rate;
Christopher Ferris05d08e92016-02-04 13:16:38 -080051 unsigned int autosync_sample_rate;
Tao Baod7db5942015-01-28 10:07:51 -080052 unsigned char system_clock_mode;
53 unsigned char clock_source;
54 unsigned char autosync_ref;
Christopher Ferris05d08e92016-02-04 13:16:38 -080055 unsigned char line_out;
Tao Baod7db5942015-01-28 10:07:51 -080056 unsigned int passthru;
57 unsigned int analog_out;
Ben Cheng655a7c02013-10-16 16:09:24 -070058};
Christopher Ferris05d08e92016-02-04 13:16:38 -080059#define SNDRV_HDSPM_IOCTL_GET_CONFIG _IOR('H', 0x41, struct hdspm_config)
Ben Cheng655a7c02013-10-16 16:09:24 -070060enum hdspm_ltc_format {
Tao Baod7db5942015-01-28 10:07:51 -080061 format_invalid,
62 fps_24,
Christopher Ferris05d08e92016-02-04 13:16:38 -080063 fps_25,
Tao Baod7db5942015-01-28 10:07:51 -080064 fps_2997,
65 fps_30
Ben Cheng655a7c02013-10-16 16:09:24 -070066};
Christopher Ferris05d08e92016-02-04 13:16:38 -080067enum hdspm_ltc_frame {
Tao Baod7db5942015-01-28 10:07:51 -080068 frame_invalid,
69 drop_frame,
70 full_frame
Christopher Ferris05d08e92016-02-04 13:16:38 -080071};
Ben Cheng655a7c02013-10-16 16:09:24 -070072enum hdspm_ltc_input_format {
Tao Baod7db5942015-01-28 10:07:51 -080073 ntsc,
74 pal,
Christopher Ferris05d08e92016-02-04 13:16:38 -080075 no_video
Ben Cheng655a7c02013-10-16 16:09:24 -070076};
77struct hdspm_ltc {
Tao Baod7db5942015-01-28 10:07:51 -080078 unsigned int ltc;
Christopher Ferris05d08e92016-02-04 13:16:38 -080079 enum hdspm_ltc_format format;
Tao Baod7db5942015-01-28 10:07:51 -080080 enum hdspm_ltc_frame frame;
81 enum hdspm_ltc_input_format input_format;
Ben Cheng655a7c02013-10-16 16:09:24 -070082};
Christopher Ferris05d08e92016-02-04 13:16:38 -080083#define SNDRV_HDSPM_IOCTL_GET_LTC _IOR('H', 0x46, struct hdspm_ltc)
Ben Cheng655a7c02013-10-16 16:09:24 -070084enum hdspm_sync {
Tao Baod7db5942015-01-28 10:07:51 -080085 hdspm_sync_no_lock = 0,
86 hdspm_sync_lock = 1,
Christopher Ferris05d08e92016-02-04 13:16:38 -080087 hdspm_sync_sync = 2
Ben Cheng655a7c02013-10-16 16:09:24 -070088};
89enum hdspm_madi_input {
Tao Baod7db5942015-01-28 10:07:51 -080090 hdspm_input_optical = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -080091 hdspm_input_coax = 1
Ben Cheng655a7c02013-10-16 16:09:24 -070092};
93enum hdspm_madi_channel_format {
Tao Baod7db5942015-01-28 10:07:51 -080094 hdspm_format_ch_64 = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -080095 hdspm_format_ch_56 = 1
Ben Cheng655a7c02013-10-16 16:09:24 -070096};
97enum hdspm_madi_frame_format {
Tao Baod7db5942015-01-28 10:07:51 -080098 hdspm_frame_48 = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -080099 hdspm_frame_96 = 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700100};
101enum hdspm_syncsource {
Tao Baod7db5942015-01-28 10:07:51 -0800102 syncsource_wc = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800103 syncsource_madi = 1,
Tao Baod7db5942015-01-28 10:07:51 -0800104 syncsource_tco = 2,
105 syncsource_sync = 3,
106 syncsource_none = 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700107};
Ben Cheng655a7c02013-10-16 16:09:24 -0700108struct hdspm_status {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800109 __u8 card_type;
Tao Baod7db5942015-01-28 10:07:51 -0800110 enum hdspm_syncsource autosync_source;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800111 __u64 card_clock;
112 __u32 master_period;
Tao Baod7db5942015-01-28 10:07:51 -0800113 union {
114 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800115 __u8 sync_wc;
116 __u8 sync_madi;
117 __u8 sync_tco;
118 __u8 sync_in;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800119 __u8 madi_input;
120 __u8 channel_format;
121 __u8 frame_format;
Tao Baod7db5942015-01-28 10:07:51 -0800122 } madi;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800123 } card_specific;
Ben Cheng655a7c02013-10-16 16:09:24 -0700124};
Tao Baod7db5942015-01-28 10:07:51 -0800125#define SNDRV_HDSPM_IOCTL_GET_STATUS _IOR('H', 0x47, struct hdspm_status)
Ben Cheng655a7c02013-10-16 16:09:24 -0700126#define HDSPM_ADDON_TCO 1
Christopher Ferris05d08e92016-02-04 13:16:38 -0800127struct hdspm_version {
128 __u8 card_type;
Tao Baod7db5942015-01-28 10:07:51 -0800129 char cardname[20];
130 unsigned int serial;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800131 unsigned short firmware_rev;
Tao Baod7db5942015-01-28 10:07:51 -0800132 int addons;
Ben Cheng655a7c02013-10-16 16:09:24 -0700133};
134#define SNDRV_HDSPM_IOCTL_GET_VERSION _IOR('H', 0x48, struct hdspm_version)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800135#define HDSPM_MIXER_CHANNELS HDSPM_MAX_CHANNELS
Ben Cheng655a7c02013-10-16 16:09:24 -0700136struct hdspm_channelfader {
Tao Baod7db5942015-01-28 10:07:51 -0800137 unsigned int in[HDSPM_MIXER_CHANNELS];
138 unsigned int pb[HDSPM_MIXER_CHANNELS];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800139};
Ben Cheng655a7c02013-10-16 16:09:24 -0700140struct hdspm_mixer {
Tao Baod7db5942015-01-28 10:07:51 -0800141 struct hdspm_channelfader ch[HDSPM_MIXER_CHANNELS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700142};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800143struct hdspm_mixer_ioctl {
Tao Baod7db5942015-01-28 10:07:51 -0800144 struct hdspm_mixer * mixer;
Ben Cheng655a7c02013-10-16 16:09:24 -0700145};
146#define SNDRV_HDSPM_IOCTL_GET_MIXER _IOR('H', 0x44, struct hdspm_mixer_ioctl)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800147typedef struct hdspm_peak_rms hdspm_peak_rms_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700148typedef struct hdspm_config_info hdspm_config_info_t;
149typedef struct hdspm_version hdspm_version_t;
150typedef struct hdspm_channelfader snd_hdspm_channelfader_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800151typedef struct hdspm_mixer hdspm_mixer_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700152#endif