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gerrit.omnirom.org / android_bionic / 12773b6ecad9970a29b60964b7780b19cb09da9f / . / libc / kernel / uapi / drm / ivpu_accel.h
blob: ca2014f38ce85b20c530786343cfe295807870c1 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +0000[diff] [blame]1/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +0000[diff] [blame]7#ifndef __UAPI_IVPU_DRM_H__
8#define __UAPI_IVPU_DRM_H__
9#include "drm.h"
10#ifdef __cplusplus
11extern "C" {
12#endif
13#define DRM_IVPU_DRIVER_MAJOR 1
14#define DRM_IVPU_DRIVER_MINOR 0
15#define DRM_IVPU_GET_PARAM 0x00
16#define DRM_IVPU_SET_PARAM 0x01
17#define DRM_IVPU_BO_CREATE 0x02
18#define DRM_IVPU_BO_INFO 0x03
19#define DRM_IVPU_SUBMIT 0x05
20#define DRM_IVPU_BO_WAIT 0x06
21#define DRM_IOCTL_IVPU_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
22#define DRM_IOCTL_IVPU_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param)
23#define DRM_IOCTL_IVPU_BO_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create)
24#define DRM_IOCTL_IVPU_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info)
25#define DRM_IOCTL_IVPU_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit)
26#define DRM_IOCTL_IVPU_BO_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait)
27#define DRM_IVPU_PARAM_DEVICE_ID 0
28#define DRM_IVPU_PARAM_DEVICE_REVISION 1
29#define DRM_IVPU_PARAM_PLATFORM_TYPE 2
30#define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3
31#define DRM_IVPU_PARAM_NUM_CONTEXTS 4
32#define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5
33#define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6
34#define DRM_IVPU_PARAM_CONTEXT_ID 7
35#define DRM_IVPU_PARAM_FW_API_VERSION 8
36#define DRM_IVPU_PARAM_ENGINE_HEARTBEAT 9
37#define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10
38#define DRM_IVPU_PARAM_TILE_CONFIG 11
39#define DRM_IVPU_PARAM_SKU 12
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700[diff] [blame]40#define DRM_IVPU_PARAM_CAPABILITIES 13
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +0000[diff] [blame]41#define DRM_IVPU_PLATFORM_TYPE_SILICON 0
42#define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0
43#define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1
44#define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
45#define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700[diff] [blame]46#define DRM_IVPU_CAP_METRIC_STREAMER 1
47#define DRM_IVPU_CAP_DMA_MEMORY_RANGE 2
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +0000[diff] [blame]48struct drm_ivpu_param {
49 __u32 param;
50 __u32 index;
51 __u64 value;
52};
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700[diff] [blame]53#define DRM_IVPU_BO_SHAVE_MEM 0x00000001
54#define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +0000[diff] [blame]55#define DRM_IVPU_BO_MAPPABLE 0x00000002
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700[diff] [blame]56#define DRM_IVPU_BO_DMA_MEM 0x00000004
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +0000[diff] [blame]57#define DRM_IVPU_BO_CACHED 0x00000000
58#define DRM_IVPU_BO_UNCACHED 0x00010000
59#define DRM_IVPU_BO_WC 0x00020000
60#define DRM_IVPU_BO_CACHE_MASK 0x00030000
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700[diff] [blame]61#define DRM_IVPU_BO_FLAGS (DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_MAPPABLE | DRM_IVPU_BO_DMA_MEM | DRM_IVPU_BO_CACHE_MASK)
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +0000[diff] [blame]62struct drm_ivpu_bo_create {
63 __u64 size;
64 __u32 flags;
65 __u32 handle;
66 __u64 vpu_addr;
67};
68struct drm_ivpu_bo_info {
69 __u32 handle;
70 __u32 flags;
71 __u64 vpu_addr;
72 __u64 mmap_offset;
73 __u64 size;
74};
75#define DRM_IVPU_ENGINE_COMPUTE 0
76#define DRM_IVPU_ENGINE_COPY 1
77struct drm_ivpu_submit {
78 __u64 buffers_ptr;
79 __u32 buffer_count;
80 __u32 engine;
81 __u32 flags;
82 __u32 commands_offset;
83};
84#define DRM_IVPU_JOB_STATUS_SUCCESS 0
85struct drm_ivpu_bo_wait {
86 __u32 handle;
87 __u32 flags;
88 __s64 timeout_ns;
89 __u32 job_status;
90 __u32 pad;
91};
92#ifdef __cplusplus
93}
94#endif
95#endif