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gerrit.omnirom.org / android_bionic / 7b85fb0d393c3119501779176b532b37182b0584 / . / libc / kernel / uapi / linux / spi / spidev.h
blob: 2fe826445b93bdc0f430c1ace269c64a6c10d69f [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef SPIDEV_H
20#define SPIDEV_H
21#include <linux/types.h>
Christopher Ferris1308ad32017-11-14 17:32:13 -0800[diff] [blame]22#include <linux/ioctl.h>
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23#define SPI_CPHA 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]24#define SPI_CPOL 0x02
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]25#define SPI_MODE_0 (0 | 0)
26#define SPI_MODE_1 (0 | SPI_CPHA)
27#define SPI_MODE_2 (SPI_CPOL | 0)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]28#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29#define SPI_CS_HIGH 0x04
30#define SPI_LSB_FIRST 0x08
31#define SPI_3WIRE 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]32#define SPI_LOOP 0x20
33#define SPI_NO_CS 0x40
34#define SPI_READY 0x80
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]35#define SPI_TX_DUAL 0x100
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]36#define SPI_TX_QUAD 0x200
37#define SPI_RX_DUAL 0x400
38#define SPI_RX_QUAD 0x800
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39#define SPI_IOC_MAGIC 'k'
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]40struct spi_ioc_transfer {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]41 __u64 tx_buf;
42 __u64 rx_buf;
43 __u32 len;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]44 __u32 speed_hz;
45 __u16 delay_usecs;
46 __u8 bits_per_word;
47 __u8 cs_change;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]48 __u8 tx_nbits;
49 __u8 rx_nbits;
50 __u16 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]51};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]52#define SPI_MSGSIZE(N) ((((N) * (sizeof(struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) ? ((N) * (sizeof(struct spi_ioc_transfer))) : 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]53#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]54#define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8)
55#define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8)
56#define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, __u8)
57#define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, __u8)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]58#define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, __u8)
59#define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, __u8)
60#define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32)
61#define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]62#define SPI_IOC_RD_MODE32 _IOR(SPI_IOC_MAGIC, 5, __u32)
63#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, __u32)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64#endif