blob: 66942e7fc5de255e06af87346f6effd1b23be271 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef OMAP3_ISP_USER_H
20#define OMAP3_ISP_USER_H
21#include <linux/types.h>
22#include <linux/videodev2.h>
Tao Baod7db5942015-01-28 10:07:51 -080023#define VIDIOC_OMAP3ISP_CCDC_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct omap3isp_ccdc_update_config)
24#define VIDIOC_OMAP3ISP_PRV_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct omap3isp_prev_update_config)
25#define VIDIOC_OMAP3ISP_AEWB_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct omap3isp_h3a_aewb_config)
26#define VIDIOC_OMAP3ISP_HIST_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct omap3isp_hist_config)
Tao Baod7db5942015-01-28 10:07:51 -080027#define VIDIOC_OMAP3ISP_AF_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct omap3isp_h3a_af_config)
28#define VIDIOC_OMAP3ISP_STAT_REQ _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct omap3isp_stat_data)
29#define VIDIOC_OMAP3ISP_STAT_EN _IOWR('V', BASE_VIDIOC_PRIVATE + 7, unsigned long)
Ben Cheng655a7c02013-10-16 16:09:24 -070030#define V4L2_EVENT_OMAP3ISP_CLASS (V4L2_EVENT_PRIVATE_START | 0x100)
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define V4L2_EVENT_OMAP3ISP_AEWB (V4L2_EVENT_OMAP3ISP_CLASS | 0x1)
32#define V4L2_EVENT_OMAP3ISP_AF (V4L2_EVENT_OMAP3ISP_CLASS | 0x2)
33#define V4L2_EVENT_OMAP3ISP_HIST (V4L2_EVENT_OMAP3ISP_CLASS | 0x3)
34struct omap3isp_stat_event_status {
Tao Baod7db5942015-01-28 10:07:51 -080035 __u32 frame_number;
36 __u16 config_counter;
37 __u8 buf_err;
Ben Cheng655a7c02013-10-16 16:09:24 -070038};
Ben Cheng655a7c02013-10-16 16:09:24 -070039#define OMAP3ISP_AEWB_MAX_SATURATION_LIM 1023
40#define OMAP3ISP_AEWB_MIN_WIN_H 2
41#define OMAP3ISP_AEWB_MAX_WIN_H 256
42#define OMAP3ISP_AEWB_MIN_WIN_W 6
Ben Cheng655a7c02013-10-16 16:09:24 -070043#define OMAP3ISP_AEWB_MAX_WIN_W 256
44#define OMAP3ISP_AEWB_MIN_WINVC 1
45#define OMAP3ISP_AEWB_MIN_WINHC 1
46#define OMAP3ISP_AEWB_MAX_WINVC 128
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define OMAP3ISP_AEWB_MAX_WINHC 36
48#define OMAP3ISP_AEWB_MAX_WINSTART 4095
49#define OMAP3ISP_AEWB_MIN_SUB_INC 2
50#define OMAP3ISP_AEWB_MAX_SUB_INC 32
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define OMAP3ISP_AEWB_MAX_BUF_SIZE 83600
52#define OMAP3ISP_AF_IIRSH_MIN 0
53#define OMAP3ISP_AF_IIRSH_MAX 4095
54#define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MIN 1
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MAX 36
56#define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MIN 1
57#define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MAX 128
58#define OMAP3ISP_AF_PAXEL_INCREMENT_MIN 2
Ben Cheng655a7c02013-10-16 16:09:24 -070059#define OMAP3ISP_AF_PAXEL_INCREMENT_MAX 32
60#define OMAP3ISP_AF_PAXEL_HEIGHT_MIN 2
61#define OMAP3ISP_AF_PAXEL_HEIGHT_MAX 256
62#define OMAP3ISP_AF_PAXEL_WIDTH_MIN 16
Ben Cheng655a7c02013-10-16 16:09:24 -070063#define OMAP3ISP_AF_PAXEL_WIDTH_MAX 256
64#define OMAP3ISP_AF_PAXEL_HZSTART_MIN 1
65#define OMAP3ISP_AF_PAXEL_HZSTART_MAX 4095
66#define OMAP3ISP_AF_PAXEL_VTSTART_MIN 0
Ben Cheng655a7c02013-10-16 16:09:24 -070067#define OMAP3ISP_AF_PAXEL_VTSTART_MAX 4095
68#define OMAP3ISP_AF_THRESHOLD_MAX 255
69#define OMAP3ISP_AF_COEF_MAX 4095
70#define OMAP3ISP_AF_PAXEL_SIZE 48
Ben Cheng655a7c02013-10-16 16:09:24 -070071#define OMAP3ISP_AF_MAX_BUF_SIZE 221184
72struct omap3isp_h3a_aewb_config {
Tao Baod7db5942015-01-28 10:07:51 -080073 __u32 buf_size;
74 __u16 config_counter;
Tao Baod7db5942015-01-28 10:07:51 -080075 __u16 saturation_limit;
76 __u16 win_height;
77 __u16 win_width;
78 __u16 ver_win_count;
Tao Baod7db5942015-01-28 10:07:51 -080079 __u16 hor_win_count;
80 __u16 ver_win_start;
81 __u16 hor_win_start;
82 __u16 blk_ver_win_start;
Tao Baod7db5942015-01-28 10:07:51 -080083 __u16 blk_win_height;
84 __u16 subsample_ver_inc;
85 __u16 subsample_hor_inc;
86 __u8 alaw_enable;
Ben Cheng655a7c02013-10-16 16:09:24 -070087};
88struct omap3isp_stat_data {
Tao Baod7db5942015-01-28 10:07:51 -080089 struct timeval ts;
90 void __user * buf;
Tao Baod7db5942015-01-28 10:07:51 -080091 __u32 buf_size;
92 __u16 frame_number;
93 __u16 cur_frame;
94 __u16 config_counter;
Ben Cheng655a7c02013-10-16 16:09:24 -070095};
96#define OMAP3ISP_HIST_BINS_32 0
97#define OMAP3ISP_HIST_BINS_64 1
98#define OMAP3ISP_HIST_BINS_128 2
Ben Cheng655a7c02013-10-16 16:09:24 -070099#define OMAP3ISP_HIST_BINS_256 3
Tao Baod7db5942015-01-28 10:07:51 -0800100#define OMAP3ISP_HIST_MEM_SIZE_BINS(n) ((1 << ((n) + 5)) * 4 * 4)
Ben Cheng655a7c02013-10-16 16:09:24 -0700101#define OMAP3ISP_HIST_MEM_SIZE 1024
102#define OMAP3ISP_HIST_MIN_REGIONS 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700103#define OMAP3ISP_HIST_MAX_REGIONS 4
104#define OMAP3ISP_HIST_MAX_WB_GAIN 255
105#define OMAP3ISP_HIST_MIN_WB_GAIN 0
106#define OMAP3ISP_HIST_MAX_BIT_WIDTH 14
Ben Cheng655a7c02013-10-16 16:09:24 -0700107#define OMAP3ISP_HIST_MIN_BIT_WIDTH 8
108#define OMAP3ISP_HIST_MAX_WG 4
109#define OMAP3ISP_HIST_MAX_BUF_SIZE 4096
110#define OMAP3ISP_HIST_SOURCE_CCDC 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700111#define OMAP3ISP_HIST_SOURCE_MEM 1
112#define OMAP3ISP_HIST_CFA_BAYER 0
113#define OMAP3ISP_HIST_CFA_FOVEONX3 1
114struct omap3isp_hist_region {
Tao Baod7db5942015-01-28 10:07:51 -0800115 __u16 h_start;
116 __u16 h_end;
117 __u16 v_start;
118 __u16 v_end;
Ben Cheng655a7c02013-10-16 16:09:24 -0700119};
120struct omap3isp_hist_config {
Tao Baod7db5942015-01-28 10:07:51 -0800121 __u32 buf_size;
122 __u16 config_counter;
Tao Baod7db5942015-01-28 10:07:51 -0800123 __u8 num_acc_frames;
124 __u16 hist_bins;
125 __u8 cfa;
126 __u8 wg[OMAP3ISP_HIST_MAX_WG];
Tao Baod7db5942015-01-28 10:07:51 -0800127 __u8 num_regions;
128 struct omap3isp_hist_region region[OMAP3ISP_HIST_MAX_REGIONS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700129};
130#define OMAP3ISP_AF_NUM_COEF 11
Ben Cheng655a7c02013-10-16 16:09:24 -0700131enum omap3isp_h3a_af_fvmode {
Tao Baod7db5942015-01-28 10:07:51 -0800132 OMAP3ISP_AF_MODE_SUMMED = 0,
133 OMAP3ISP_AF_MODE_PEAK = 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700134};
Ben Cheng655a7c02013-10-16 16:09:24 -0700135enum omap3isp_h3a_af_rgbpos {
Tao Baod7db5942015-01-28 10:07:51 -0800136 OMAP3ISP_AF_GR_GB_BAYER = 0,
137 OMAP3ISP_AF_RG_GB_BAYER = 1,
138 OMAP3ISP_AF_GR_BG_BAYER = 2,
Tao Baod7db5942015-01-28 10:07:51 -0800139 OMAP3ISP_AF_RG_BG_BAYER = 3,
140 OMAP3ISP_AF_GG_RB_CUSTOM = 4,
141 OMAP3ISP_AF_RB_GG_CUSTOM = 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700142};
Ben Cheng655a7c02013-10-16 16:09:24 -0700143struct omap3isp_h3a_af_hmf {
Tao Baod7db5942015-01-28 10:07:51 -0800144 __u8 enable;
145 __u8 threshold;
Ben Cheng655a7c02013-10-16 16:09:24 -0700146};
Ben Cheng655a7c02013-10-16 16:09:24 -0700147struct omap3isp_h3a_af_iir {
Tao Baod7db5942015-01-28 10:07:51 -0800148 __u16 h_start;
149 __u16 coeff_set0[OMAP3ISP_AF_NUM_COEF];
150 __u16 coeff_set1[OMAP3ISP_AF_NUM_COEF];
Ben Cheng655a7c02013-10-16 16:09:24 -0700151};
152struct omap3isp_h3a_af_paxel {
Tao Baod7db5942015-01-28 10:07:51 -0800153 __u16 h_start;
154 __u16 v_start;
Tao Baod7db5942015-01-28 10:07:51 -0800155 __u8 width;
156 __u8 height;
157 __u8 h_cnt;
158 __u8 v_cnt;
Tao Baod7db5942015-01-28 10:07:51 -0800159 __u8 line_inc;
Ben Cheng655a7c02013-10-16 16:09:24 -0700160};
161struct omap3isp_h3a_af_config {
Tao Baod7db5942015-01-28 10:07:51 -0800162 __u32 buf_size;
Tao Baod7db5942015-01-28 10:07:51 -0800163 __u16 config_counter;
164 struct omap3isp_h3a_af_hmf hmf;
165 struct omap3isp_h3a_af_iir iir;
166 struct omap3isp_h3a_af_paxel paxel;
Tao Baod7db5942015-01-28 10:07:51 -0800167 enum omap3isp_h3a_af_rgbpos rgb_pos;
168 enum omap3isp_h3a_af_fvmode fvmode;
169 __u8 alaw_enable;
Ben Cheng655a7c02013-10-16 16:09:24 -0700170};
Ben Cheng655a7c02013-10-16 16:09:24 -0700171#define OMAP3ISP_CCDC_ALAW (1 << 0)
172#define OMAP3ISP_CCDC_LPF (1 << 1)
173#define OMAP3ISP_CCDC_BLCLAMP (1 << 2)
174#define OMAP3ISP_CCDC_BCOMP (1 << 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700175#define OMAP3ISP_CCDC_FPC (1 << 4)
176#define OMAP3ISP_CCDC_CULL (1 << 5)
177#define OMAP3ISP_CCDC_CONFIG_LSC (1 << 7)
178#define OMAP3ISP_CCDC_TBL_LSC (1 << 8)
Ben Cheng655a7c02013-10-16 16:09:24 -0700179#define OMAP3ISP_RGB_MAX 3
180enum omap3isp_alaw_ipwidth {
Tao Baod7db5942015-01-28 10:07:51 -0800181 OMAP3ISP_ALAW_BIT12_3 = 0x3,
182 OMAP3ISP_ALAW_BIT11_2 = 0x4,
Tao Baod7db5942015-01-28 10:07:51 -0800183 OMAP3ISP_ALAW_BIT10_1 = 0x5,
184 OMAP3ISP_ALAW_BIT9_0 = 0x6
Ben Cheng655a7c02013-10-16 16:09:24 -0700185};
186struct omap3isp_ccdc_lsc_config {
Tao Baod7db5942015-01-28 10:07:51 -0800187 __u16 offset;
188 __u8 gain_mode_n;
189 __u8 gain_mode_m;
190 __u8 gain_format;
Tao Baod7db5942015-01-28 10:07:51 -0800191 __u16 fmtsph;
192 __u16 fmtlnh;
193 __u16 fmtslv;
194 __u16 fmtlnv;
Tao Baod7db5942015-01-28 10:07:51 -0800195 __u8 initial_x;
196 __u8 initial_y;
197 __u32 size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700198};
Ben Cheng655a7c02013-10-16 16:09:24 -0700199struct omap3isp_ccdc_bclamp {
Tao Baod7db5942015-01-28 10:07:51 -0800200 __u8 obgain;
201 __u8 obstpixel;
202 __u8 oblines;
Tao Baod7db5942015-01-28 10:07:51 -0800203 __u8 oblen;
204 __u16 dcsubval;
Ben Cheng655a7c02013-10-16 16:09:24 -0700205};
206struct omap3isp_ccdc_fpc {
Tao Baod7db5942015-01-28 10:07:51 -0800207 __u16 fpnum;
208 __u32 fpcaddr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700209};
210struct omap3isp_ccdc_blcomp {
Tao Baod7db5942015-01-28 10:07:51 -0800211 __u8 b_mg;
212 __u8 gb_g;
213 __u8 gr_cy;
214 __u8 r_ye;
Ben Cheng655a7c02013-10-16 16:09:24 -0700215};
216struct omap3isp_ccdc_culling {
Tao Baod7db5942015-01-28 10:07:51 -0800217 __u8 v_pattern;
218 __u16 h_odd;
Tao Baod7db5942015-01-28 10:07:51 -0800219 __u16 h_even;
Ben Cheng655a7c02013-10-16 16:09:24 -0700220};
221struct omap3isp_ccdc_update_config {
Tao Baod7db5942015-01-28 10:07:51 -0800222 __u16 update;
Tao Baod7db5942015-01-28 10:07:51 -0800223 __u16 flag;
224 enum omap3isp_alaw_ipwidth alawip;
225 struct omap3isp_ccdc_bclamp __user * bclamp;
226 struct omap3isp_ccdc_blcomp __user * blcomp;
Tao Baod7db5942015-01-28 10:07:51 -0800227 struct omap3isp_ccdc_fpc __user * fpc;
228 struct omap3isp_ccdc_lsc_config __user * lsc_cfg;
229 struct omap3isp_ccdc_culling __user * cull;
230 __u8 __user * lsc;
Ben Cheng655a7c02013-10-16 16:09:24 -0700231};
232#define OMAP3ISP_PREV_LUMAENH (1 << 0)
233#define OMAP3ISP_PREV_INVALAW (1 << 1)
234#define OMAP3ISP_PREV_HRZ_MED (1 << 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700235#define OMAP3ISP_PREV_CFA (1 << 3)
236#define OMAP3ISP_PREV_CHROMA_SUPP (1 << 4)
237#define OMAP3ISP_PREV_WB (1 << 5)
238#define OMAP3ISP_PREV_BLKADJ (1 << 6)
Ben Cheng655a7c02013-10-16 16:09:24 -0700239#define OMAP3ISP_PREV_RGB2RGB (1 << 7)
240#define OMAP3ISP_PREV_COLOR_CONV (1 << 8)
241#define OMAP3ISP_PREV_YC_LIMIT (1 << 9)
242#define OMAP3ISP_PREV_DEFECT_COR (1 << 10)
Ben Cheng655a7c02013-10-16 16:09:24 -0700243#define OMAP3ISP_PREV_DRK_FRM_CAPTURE (1 << 12)
244#define OMAP3ISP_PREV_DRK_FRM_SUBTRACT (1 << 13)
245#define OMAP3ISP_PREV_LENS_SHADING (1 << 14)
246#define OMAP3ISP_PREV_NF (1 << 15)
Ben Cheng655a7c02013-10-16 16:09:24 -0700247#define OMAP3ISP_PREV_GAMMA (1 << 16)
248#define OMAP3ISP_PREV_NF_TBL_SIZE 64
249#define OMAP3ISP_PREV_CFA_TBL_SIZE 576
250#define OMAP3ISP_PREV_CFA_BLK_SIZE (OMAP3ISP_PREV_CFA_TBL_SIZE / 4)
Ben Cheng655a7c02013-10-16 16:09:24 -0700251#define OMAP3ISP_PREV_GAMMA_TBL_SIZE 1024
252#define OMAP3ISP_PREV_YENH_TBL_SIZE 128
253#define OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS 4
254struct omap3isp_prev_hmed {
Tao Baod7db5942015-01-28 10:07:51 -0800255 __u8 odddist;
256 __u8 evendist;
257 __u8 thres;
Ben Cheng655a7c02013-10-16 16:09:24 -0700258};
Ben Cheng655a7c02013-10-16 16:09:24 -0700259enum omap3isp_cfa_fmt {
Tao Baod7db5942015-01-28 10:07:51 -0800260 OMAP3ISP_CFAFMT_BAYER,
261 OMAP3ISP_CFAFMT_SONYVGA,
262 OMAP3ISP_CFAFMT_RGBFOVEON,
Tao Baod7db5942015-01-28 10:07:51 -0800263 OMAP3ISP_CFAFMT_DNSPL,
264 OMAP3ISP_CFAFMT_HONEYCOMB,
265 OMAP3ISP_CFAFMT_RRGGBBFOVEON
Ben Cheng655a7c02013-10-16 16:09:24 -0700266};
Ben Cheng655a7c02013-10-16 16:09:24 -0700267struct omap3isp_prev_cfa {
Tao Baod7db5942015-01-28 10:07:51 -0800268 enum omap3isp_cfa_fmt format;
269 __u8 gradthrs_vert;
270 __u8 gradthrs_horz;
Tao Baod7db5942015-01-28 10:07:51 -0800271 __u32 table[4][OMAP3ISP_PREV_CFA_BLK_SIZE];
Ben Cheng655a7c02013-10-16 16:09:24 -0700272};
273struct omap3isp_prev_csup {
Tao Baod7db5942015-01-28 10:07:51 -0800274 __u8 gain;
Tao Baod7db5942015-01-28 10:07:51 -0800275 __u8 thres;
276 __u8 hypf_en;
Ben Cheng655a7c02013-10-16 16:09:24 -0700277};
278struct omap3isp_prev_wbal {
Tao Baod7db5942015-01-28 10:07:51 -0800279 __u16 dgain;
280 __u8 coef3;
281 __u8 coef2;
282 __u8 coef1;
Tao Baod7db5942015-01-28 10:07:51 -0800283 __u8 coef0;
Ben Cheng655a7c02013-10-16 16:09:24 -0700284};
285struct omap3isp_prev_blkadj {
Tao Baod7db5942015-01-28 10:07:51 -0800286 __u8 red;
Tao Baod7db5942015-01-28 10:07:51 -0800287 __u8 green;
288 __u8 blue;
Ben Cheng655a7c02013-10-16 16:09:24 -0700289};
290struct omap3isp_prev_rgbtorgb {
Tao Baod7db5942015-01-28 10:07:51 -0800291 __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX];
292 __u16 offset[OMAP3ISP_RGB_MAX];
Ben Cheng655a7c02013-10-16 16:09:24 -0700293};
294struct omap3isp_prev_csc {
Tao Baod7db5942015-01-28 10:07:51 -0800295 __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX];
296 __s16 offset[OMAP3ISP_RGB_MAX];
Ben Cheng655a7c02013-10-16 16:09:24 -0700297};
298struct omap3isp_prev_yclimit {
Tao Baod7db5942015-01-28 10:07:51 -0800299 __u8 minC;
300 __u8 maxC;
301 __u8 minY;
302 __u8 maxY;
Ben Cheng655a7c02013-10-16 16:09:24 -0700303};
304struct omap3isp_prev_dcor {
Tao Baod7db5942015-01-28 10:07:51 -0800305 __u8 couplet_mode_en;
306 __u32 detect_correct[OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700307};
308struct omap3isp_prev_nf {
Tao Baod7db5942015-01-28 10:07:51 -0800309 __u8 spread;
310 __u32 table[OMAP3ISP_PREV_NF_TBL_SIZE];
Ben Cheng655a7c02013-10-16 16:09:24 -0700311};
312struct omap3isp_prev_gtables {
Tao Baod7db5942015-01-28 10:07:51 -0800313 __u32 red[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
314 __u32 green[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
Tao Baod7db5942015-01-28 10:07:51 -0800315 __u32 blue[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
Ben Cheng655a7c02013-10-16 16:09:24 -0700316};
317struct omap3isp_prev_luma {
Tao Baod7db5942015-01-28 10:07:51 -0800318 __u32 table[OMAP3ISP_PREV_YENH_TBL_SIZE];
Ben Cheng655a7c02013-10-16 16:09:24 -0700319};
320struct omap3isp_prev_update_config {
Tao Baod7db5942015-01-28 10:07:51 -0800321 __u32 update;
322 __u32 flag;
Tao Baod7db5942015-01-28 10:07:51 -0800323 __u32 shading_shift;
324 struct omap3isp_prev_luma __user * luma;
325 struct omap3isp_prev_hmed __user * hmed;
326 struct omap3isp_prev_cfa __user * cfa;
Tao Baod7db5942015-01-28 10:07:51 -0800327 struct omap3isp_prev_csup __user * csup;
328 struct omap3isp_prev_wbal __user * wbal;
329 struct omap3isp_prev_blkadj __user * blkadj;
330 struct omap3isp_prev_rgbtorgb __user * rgb2rgb;
Tao Baod7db5942015-01-28 10:07:51 -0800331 struct omap3isp_prev_csc __user * csc;
332 struct omap3isp_prev_yclimit __user * yclimit;
333 struct omap3isp_prev_dcor __user * dcor;
334 struct omap3isp_prev_nf __user * nf;
Tao Baod7db5942015-01-28 10:07:51 -0800335 struct omap3isp_prev_gtables __user * gamma;
Ben Cheng655a7c02013-10-16 16:09:24 -0700336};
337#endif