blob: dcc382646b68eeae74e040515e71a1346d591956 [file] [log] [blame]
Ben Chenga6b53f02013-11-06 15:51:05 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI__ASM_ARM_PTRACE_H
20#define _UAPI__ASM_ARM_PTRACE_H
21#include <asm/hwcap.h>
22#define PTRACE_GETREGS 12
Ben Chenga6b53f02013-11-06 15:51:05 -080023#define PTRACE_SETREGS 13
24#define PTRACE_GETFPREGS 14
25#define PTRACE_SETFPREGS 15
26#define PTRACE_GETWMMXREGS 18
Ben Chenga6b53f02013-11-06 15:51:05 -080027#define PTRACE_SETWMMXREGS 19
28#define PTRACE_OLDSETOPTIONS 21
29#define PTRACE_GET_THREAD_AREA 22
30#define PTRACE_SET_SYSCALL 23
Ben Chenga6b53f02013-11-06 15:51:05 -080031#define PTRACE_GETCRUNCHREGS 25
32#define PTRACE_SETCRUNCHREGS 26
33#define PTRACE_GETVFPREGS 27
34#define PTRACE_SETVFPREGS 28
Ben Chenga6b53f02013-11-06 15:51:05 -080035#define PTRACE_GETHBPREGS 29
36#define PTRACE_SETHBPREGS 30
37#define USR26_MODE 0x00000000
38#define FIQ26_MODE 0x00000001
Ben Chenga6b53f02013-11-06 15:51:05 -080039#define IRQ26_MODE 0x00000002
40#define SVC26_MODE 0x00000003
41#define USR_MODE 0x00000010
Elliott Hughes8cb52b02013-11-21 13:43:23 -080042#define SVC_MODE 0x00000013
Christopher Ferris38062f92014-07-09 15:33:25 -070043#define FIQ_MODE 0x00000011
44#define IRQ_MODE 0x00000012
Ben Chenga6b53f02013-11-06 15:51:05 -080045#define ABT_MODE 0x00000017
46#define HYP_MODE 0x0000001a
Ben Chenga6b53f02013-11-06 15:51:05 -080047#define UND_MODE 0x0000001b
48#define SYSTEM_MODE 0x0000001f
49#define MODE32_BIT 0x00000010
50#define MODE_MASK 0x0000001f
Christopher Ferris38062f92014-07-09 15:33:25 -070051#define V4_PSR_T_BIT 0x00000020
52#define V7M_PSR_T_BIT 0x01000000
53#define PSR_T_BIT V4_PSR_T_BIT
Ben Chenga6b53f02013-11-06 15:51:05 -080054#define PSR_F_BIT 0x00000040
Ben Chenga6b53f02013-11-06 15:51:05 -080055#define PSR_I_BIT 0x00000080
56#define PSR_A_BIT 0x00000100
57#define PSR_E_BIT 0x00000200
58#define PSR_J_BIT 0x01000000
Ben Chenga6b53f02013-11-06 15:51:05 -080059#define PSR_Q_BIT 0x08000000
60#define PSR_V_BIT 0x10000000
61#define PSR_C_BIT 0x20000000
62#define PSR_Z_BIT 0x40000000
Ben Chenga6b53f02013-11-06 15:51:05 -080063#define PSR_N_BIT 0x80000000
64#define PSR_f 0xff000000
65#define PSR_s 0x00ff0000
66#define PSR_x 0x0000ff00
Ben Chenga6b53f02013-11-06 15:51:05 -080067#define PSR_c 0x000000ff
68#define APSR_MASK 0xf80f0000
69#define PSR_ISET_MASK 0x01000010
70#define PSR_IT_MASK 0x0600fc00
Ben Chenga6b53f02013-11-06 15:51:05 -080071#define PSR_ENDIAN_MASK 0x00000200
72#define PSR_ENDSTATE 0
73#define PT_TEXT_ADDR 0x10000
74#define PT_DATA_ADDR 0x10004
Ben Chenga6b53f02013-11-06 15:51:05 -080075#define PT_TEXT_END_ADDR 0x10008
76#ifndef __ASSEMBLY__
77struct pt_regs {
Tao Baod7db5942015-01-28 10:07:51 -080078 long uregs[18];
Ben Chenga6b53f02013-11-06 15:51:05 -080079};
80#define ARM_cpsr uregs[16]
81#define ARM_pc uregs[15]
82#define ARM_lr uregs[14]
Ben Chenga6b53f02013-11-06 15:51:05 -080083#define ARM_sp uregs[13]
84#define ARM_ip uregs[12]
85#define ARM_fp uregs[11]
86#define ARM_r10 uregs[10]
Ben Chenga6b53f02013-11-06 15:51:05 -080087#define ARM_r9 uregs[9]
88#define ARM_r8 uregs[8]
89#define ARM_r7 uregs[7]
90#define ARM_r6 uregs[6]
Ben Chenga6b53f02013-11-06 15:51:05 -080091#define ARM_r5 uregs[5]
92#define ARM_r4 uregs[4]
93#define ARM_r3 uregs[3]
94#define ARM_r2 uregs[2]
Ben Chenga6b53f02013-11-06 15:51:05 -080095#define ARM_r1 uregs[1]
96#define ARM_r0 uregs[0]
97#define ARM_ORIG_r0 uregs[17]
Tao Baod7db5942015-01-28 10:07:51 -080098#define ARM_VFPREGS_SIZE (32 * 8 + 4)
Christopher Ferris38062f92014-07-09 15:33:25 -070099#endif
100#endif