blob: e148a5b7a2aeffbdcea1096c3bd75af789fff3cc [file] [log] [blame]
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +00001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __UAPI_IVPU_DRM_H__
20#define __UAPI_IVPU_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
23extern "C" {
24#endif
25#define DRM_IVPU_DRIVER_MAJOR 1
26#define DRM_IVPU_DRIVER_MINOR 0
27#define DRM_IVPU_GET_PARAM 0x00
28#define DRM_IVPU_SET_PARAM 0x01
29#define DRM_IVPU_BO_CREATE 0x02
30#define DRM_IVPU_BO_INFO 0x03
31#define DRM_IVPU_SUBMIT 0x05
32#define DRM_IVPU_BO_WAIT 0x06
33#define DRM_IOCTL_IVPU_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
34#define DRM_IOCTL_IVPU_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param)
35#define DRM_IOCTL_IVPU_BO_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create)
36#define DRM_IOCTL_IVPU_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info)
37#define DRM_IOCTL_IVPU_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit)
38#define DRM_IOCTL_IVPU_BO_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait)
39#define DRM_IVPU_PARAM_DEVICE_ID 0
40#define DRM_IVPU_PARAM_DEVICE_REVISION 1
41#define DRM_IVPU_PARAM_PLATFORM_TYPE 2
42#define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3
43#define DRM_IVPU_PARAM_NUM_CONTEXTS 4
44#define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5
45#define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6
46#define DRM_IVPU_PARAM_CONTEXT_ID 7
47#define DRM_IVPU_PARAM_FW_API_VERSION 8
48#define DRM_IVPU_PARAM_ENGINE_HEARTBEAT 9
49#define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10
50#define DRM_IVPU_PARAM_TILE_CONFIG 11
51#define DRM_IVPU_PARAM_SKU 12
52#define DRM_IVPU_PLATFORM_TYPE_SILICON 0
53#define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0
54#define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1
55#define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
56#define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
57struct drm_ivpu_param {
58 __u32 param;
59 __u32 index;
60 __u64 value;
61};
62#define DRM_IVPU_BO_HIGH_MEM 0x00000001
63#define DRM_IVPU_BO_MAPPABLE 0x00000002
64#define DRM_IVPU_BO_CACHED 0x00000000
65#define DRM_IVPU_BO_UNCACHED 0x00010000
66#define DRM_IVPU_BO_WC 0x00020000
67#define DRM_IVPU_BO_CACHE_MASK 0x00030000
68#define DRM_IVPU_BO_FLAGS (DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_MAPPABLE | DRM_IVPU_BO_CACHE_MASK)
69struct drm_ivpu_bo_create {
70 __u64 size;
71 __u32 flags;
72 __u32 handle;
73 __u64 vpu_addr;
74};
75struct drm_ivpu_bo_info {
76 __u32 handle;
77 __u32 flags;
78 __u64 vpu_addr;
79 __u64 mmap_offset;
80 __u64 size;
81};
82#define DRM_IVPU_ENGINE_COMPUTE 0
83#define DRM_IVPU_ENGINE_COPY 1
84struct drm_ivpu_submit {
85 __u64 buffers_ptr;
86 __u32 buffer_count;
87 __u32 engine;
88 __u32 flags;
89 __u32 commands_offset;
90};
91#define DRM_IVPU_JOB_STATUS_SUCCESS 0
92struct drm_ivpu_bo_wait {
93 __u32 handle;
94 __u32 flags;
95 __s64 timeout_ns;
96 __u32 job_status;
97 __u32 pad;
98};
99#ifdef __cplusplus
100}
101#endif
102#endif