blob: c3e58cb880c427190715def8af464cc814643668 [file] [log] [blame]
Christopher Ferris9ce28842018-10-25 12:11:39 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _V3D_DRM_H_
20#define _V3D_DRM_H_
21#include "drm.h"
22#ifdef __cplusplus
23#endif
24#define DRM_V3D_SUBMIT_CL 0x00
25#define DRM_V3D_WAIT_BO 0x01
26#define DRM_V3D_CREATE_BO 0x02
27#define DRM_V3D_MMAP_BO 0x03
28#define DRM_V3D_GET_PARAM 0x04
29#define DRM_V3D_GET_BO_OFFSET 0x05
30#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
31#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
32#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
33#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
34#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
35#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
36struct drm_v3d_submit_cl {
37 __u32 bcl_start;
38 __u32 bcl_end;
39 __u32 rcl_start;
40 __u32 rcl_end;
41 __u32 in_sync_bcl;
42 __u32 in_sync_rcl;
43 __u32 out_sync;
44 __u32 qma;
45 __u32 qms;
46 __u32 qts;
47 __u64 bo_handles;
48 __u32 bo_handle_count;
49 __u32 pad;
50};
51struct drm_v3d_wait_bo {
52 __u32 handle;
53 __u32 pad;
54 __u64 timeout_ns;
55};
56struct drm_v3d_create_bo {
57 __u32 size;
58 __u32 flags;
59 __u32 handle;
60 __u32 offset;
61};
62struct drm_v3d_mmap_bo {
63 __u32 handle;
64 __u32 flags;
65 __u64 offset;
66};
67enum drm_v3d_param {
68 DRM_V3D_PARAM_V3D_UIFCFG,
69 DRM_V3D_PARAM_V3D_HUB_IDENT1,
70 DRM_V3D_PARAM_V3D_HUB_IDENT2,
71 DRM_V3D_PARAM_V3D_HUB_IDENT3,
72 DRM_V3D_PARAM_V3D_CORE0_IDENT0,
73 DRM_V3D_PARAM_V3D_CORE0_IDENT1,
74 DRM_V3D_PARAM_V3D_CORE0_IDENT2,
75};
76struct drm_v3d_get_param {
77 __u32 param;
78 __u32 pad;
79 __u64 value;
80};
81struct drm_v3d_get_bo_offset {
82 __u32 handle;
83 __u32 offset;
84};
85#ifdef __cplusplus
86#endif
87#endif