blob: 85dea7e6997d396996b0eece65d66b2658c51caa [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __R128_DRM_H__
20#define __R128_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris106b3a82016-08-24 12:15:38 -070023#endif
24#ifndef __R128_SAREA_DEFINES__
Christopher Ferris05d08e92016-02-04 13:16:38 -080025#define __R128_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -070026#define R128_UPLOAD_CONTEXT 0x001
27#define R128_UPLOAD_SETUP 0x002
28#define R128_UPLOAD_TEX0 0x004
Christopher Ferris05d08e92016-02-04 13:16:38 -080029#define R128_UPLOAD_TEX1 0x008
Ben Cheng655a7c02013-10-16 16:09:24 -070030#define R128_UPLOAD_TEX0IMAGES 0x010
31#define R128_UPLOAD_TEX1IMAGES 0x020
32#define R128_UPLOAD_CORE 0x040
Christopher Ferris05d08e92016-02-04 13:16:38 -080033#define R128_UPLOAD_MASKS 0x080
Ben Cheng655a7c02013-10-16 16:09:24 -070034#define R128_UPLOAD_WINDOW 0x100
35#define R128_UPLOAD_CLIPRECTS 0x200
36#define R128_REQUIRE_QUIESCENCE 0x400
Christopher Ferris05d08e92016-02-04 13:16:38 -080037#define R128_UPLOAD_ALL 0x7ff
Ben Cheng655a7c02013-10-16 16:09:24 -070038#define R128_FRONT 0x1
39#define R128_BACK 0x2
40#define R128_DEPTH 0x4
Christopher Ferris05d08e92016-02-04 13:16:38 -080041#define R128_POINTS 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -070042#define R128_LINES 0x2
43#define R128_LINE_STRIP 0x3
44#define R128_TRIANGLES 0x4
Christopher Ferris05d08e92016-02-04 13:16:38 -080045#define R128_TRIANGLE_FAN 0x5
Ben Cheng655a7c02013-10-16 16:09:24 -070046#define R128_TRIANGLE_STRIP 0x6
47#define R128_BUFFER_SIZE 16384
48#define R128_INDEX_PRIM_OFFSET 20
Christopher Ferris05d08e92016-02-04 13:16:38 -080049#define R128_HOSTDATA_BLIT_OFFSET 32
Ben Cheng655a7c02013-10-16 16:09:24 -070050#define R128_NR_SAREA_CLIPRECTS 12
51#define R128_LOCAL_TEX_HEAP 0
52#define R128_AGP_TEX_HEAP 1
Christopher Ferris05d08e92016-02-04 13:16:38 -080053#define R128_NR_TEX_HEAPS 2
Ben Cheng655a7c02013-10-16 16:09:24 -070054#define R128_NR_TEX_REGIONS 64
55#define R128_LOG_TEX_GRANULARITY 16
56#define R128_NR_CONTEXT_REGS 12
Christopher Ferris05d08e92016-02-04 13:16:38 -080057#define R128_MAX_TEXTURE_LEVELS 11
Ben Cheng655a7c02013-10-16 16:09:24 -070058#define R128_MAX_TEXTURE_UNITS 2
59#endif
60typedef struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -080061 unsigned int dst_pitch_offset_c;
Tao Baod7db5942015-01-28 10:07:51 -080062 unsigned int dp_gui_master_cntl_c;
63 unsigned int sc_top_left_c;
64 unsigned int sc_bottom_right_c;
Christopher Ferris05d08e92016-02-04 13:16:38 -080065 unsigned int z_offset_c;
Tao Baod7db5942015-01-28 10:07:51 -080066 unsigned int z_pitch_c;
67 unsigned int z_sten_cntl_c;
68 unsigned int tex_cntl_c;
Christopher Ferris05d08e92016-02-04 13:16:38 -080069 unsigned int misc_3d_state_cntl_reg;
Tao Baod7db5942015-01-28 10:07:51 -080070 unsigned int texture_clr_cmp_clr_c;
71 unsigned int texture_clr_cmp_msk_c;
72 unsigned int fog_color_c;
Christopher Ferris05d08e92016-02-04 13:16:38 -080073 unsigned int tex_size_pitch_c;
Tao Baod7db5942015-01-28 10:07:51 -080074 unsigned int constant_color_c;
75 unsigned int pm4_vc_fpu_setup;
76 unsigned int setup_cntl;
Christopher Ferris05d08e92016-02-04 13:16:38 -080077 unsigned int dp_write_mask;
Tao Baod7db5942015-01-28 10:07:51 -080078 unsigned int sten_ref_mask_c;
79 unsigned int plane_3d_mask_c;
80 unsigned int window_xy_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -080081 unsigned int scale_3d_cntl;
Ben Cheng655a7c02013-10-16 16:09:24 -070082} drm_r128_context_regs_t;
83typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -080084 unsigned int tex_cntl;
Christopher Ferris05d08e92016-02-04 13:16:38 -080085 unsigned int tex_combine_cntl;
Tao Baod7db5942015-01-28 10:07:51 -080086 unsigned int tex_size_pitch;
87 unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
88 unsigned int tex_border_color;
Christopher Ferris05d08e92016-02-04 13:16:38 -080089} drm_r128_texture_regs_t;
Ben Cheng655a7c02013-10-16 16:09:24 -070090typedef struct drm_r128_sarea {
Tao Baod7db5942015-01-28 10:07:51 -080091 drm_r128_context_regs_t context_state;
92 drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
Christopher Ferris05d08e92016-02-04 13:16:38 -080093 unsigned int dirty;
Tao Baod7db5942015-01-28 10:07:51 -080094 unsigned int vertsize;
95 unsigned int vc_format;
96 struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
Christopher Ferris05d08e92016-02-04 13:16:38 -080097 unsigned int nbox;
Tao Baod7db5942015-01-28 10:07:51 -080098 unsigned int last_frame;
99 unsigned int last_dispatch;
100 struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800101 unsigned int tex_age[R128_NR_TEX_HEAPS];
Tao Baod7db5942015-01-28 10:07:51 -0800102 int ctx_owner;
103 int pfAllowPageFlip;
104 int pfCurrentPage;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800105} drm_r128_sarea_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700106#define DRM_R128_INIT 0x00
107#define DRM_R128_CCE_START 0x01
108#define DRM_R128_CCE_STOP 0x02
Christopher Ferris05d08e92016-02-04 13:16:38 -0800109#define DRM_R128_CCE_RESET 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700110#define DRM_R128_CCE_IDLE 0x04
111#define DRM_R128_RESET 0x06
112#define DRM_R128_SWAP 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800113#define DRM_R128_CLEAR 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700114#define DRM_R128_VERTEX 0x09
115#define DRM_R128_INDICES 0x0a
116#define DRM_R128_BLIT 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800117#define DRM_R128_DEPTH 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700118#define DRM_R128_STIPPLE 0x0d
119#define DRM_R128_INDIRECT 0x0f
120#define DRM_R128_FULLSCREEN 0x10
Christopher Ferris05d08e92016-02-04 13:16:38 -0800121#define DRM_R128_CLEAR2 0x11
Ben Cheng655a7c02013-10-16 16:09:24 -0700122#define DRM_R128_GETPARAM 0x12
123#define DRM_R128_FLIP 0x13
Tao Baod7db5942015-01-28 10:07:51 -0800124#define DRM_IOCTL_R128_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800125#define DRM_IOCTL_R128_CCE_START DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_START)
Tao Baod7db5942015-01-28 10:07:51 -0800126#define DRM_IOCTL_R128_CCE_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
127#define DRM_IOCTL_R128_CCE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
128#define DRM_IOCTL_R128_CCE_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800129#define DRM_IOCTL_R128_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_RESET)
Tao Baod7db5942015-01-28 10:07:51 -0800130#define DRM_IOCTL_R128_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_R128_SWAP)
131#define DRM_IOCTL_R128_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
132#define DRM_IOCTL_R128_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800133#define DRM_IOCTL_R128_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
Tao Baod7db5942015-01-28 10:07:51 -0800134#define DRM_IOCTL_R128_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
135#define DRM_IOCTL_R128_DEPTH DRM_IOW(DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
136#define DRM_IOCTL_R128_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800137#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
Tao Baod7db5942015-01-28 10:07:51 -0800138#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
139#define DRM_IOCTL_R128_CLEAR2 DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
140#define DRM_IOCTL_R128_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800141#define DRM_IOCTL_R128_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_R128_FLIP)
Ben Cheng655a7c02013-10-16 16:09:24 -0700142typedef struct drm_r128_init {
Tao Baod7db5942015-01-28 10:07:51 -0800143 enum {
144 R128_INIT_CCE = 0x01,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800145 R128_CLEANUP_CCE = 0x02
Tao Baod7db5942015-01-28 10:07:51 -0800146 } func;
147 unsigned long sarea_priv_offset;
148 int is_pci;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800149 int cce_mode;
Tao Baod7db5942015-01-28 10:07:51 -0800150 int cce_secure;
151 int ring_size;
152 int usec_timeout;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800153 unsigned int fb_bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800154 unsigned int front_offset, front_pitch;
155 unsigned int back_offset, back_pitch;
156 unsigned int depth_bpp;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800157 unsigned int depth_offset, depth_pitch;
Tao Baod7db5942015-01-28 10:07:51 -0800158 unsigned int span_offset;
159 unsigned long fb_offset;
160 unsigned long mmio_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800161 unsigned long ring_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800162 unsigned long ring_rptr_offset;
163 unsigned long buffers_offset;
164 unsigned long agp_textures_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800165} drm_r128_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700166typedef struct drm_r128_cce_stop {
Tao Baod7db5942015-01-28 10:07:51 -0800167 int flush;
168 int idle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800169} drm_r128_cce_stop_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700170typedef struct drm_r128_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800171 unsigned int flags;
172 unsigned int clear_color;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800173 unsigned int clear_depth;
Tao Baod7db5942015-01-28 10:07:51 -0800174 unsigned int color_mask;
175 unsigned int depth_mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700176} drm_r128_clear_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800177typedef struct drm_r128_vertex {
Tao Baod7db5942015-01-28 10:07:51 -0800178 int prim;
179 int idx;
180 int count;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800181 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700182} drm_r128_vertex_t;
183typedef struct drm_r128_indices {
Tao Baod7db5942015-01-28 10:07:51 -0800184 int prim;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800185 int idx;
Tao Baod7db5942015-01-28 10:07:51 -0800186 int start;
187 int end;
188 int discard;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800189} drm_r128_indices_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700190typedef struct drm_r128_blit {
Tao Baod7db5942015-01-28 10:07:51 -0800191 int idx;
192 int pitch;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800193 int offset;
Tao Baod7db5942015-01-28 10:07:51 -0800194 int format;
195 unsigned short x, y;
196 unsigned short width, height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800197} drm_r128_blit_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700198typedef struct drm_r128_depth {
Tao Baod7db5942015-01-28 10:07:51 -0800199 enum {
200 R128_WRITE_SPAN = 0x01,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800201 R128_WRITE_PIXELS = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800202 R128_READ_SPAN = 0x03,
203 R128_READ_PIXELS = 0x04
204 } func;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800205 int n;
Tao Baod7db5942015-01-28 10:07:51 -0800206 int __user * x;
207 int __user * y;
208 unsigned int __user * buffer;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800209 unsigned char __user * mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700210} drm_r128_depth_t;
211typedef struct drm_r128_stipple {
Tao Baod7db5942015-01-28 10:07:51 -0800212 unsigned int __user * mask;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800213} drm_r128_stipple_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700214typedef struct drm_r128_indirect {
Tao Baod7db5942015-01-28 10:07:51 -0800215 int idx;
216 int start;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800217 int end;
Tao Baod7db5942015-01-28 10:07:51 -0800218 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700219} drm_r128_indirect_t;
220typedef struct drm_r128_fullscreen {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800221 enum {
Tao Baod7db5942015-01-28 10:07:51 -0800222 R128_INIT_FULLSCREEN = 0x01,
223 R128_CLEANUP_FULLSCREEN = 0x02
224 } func;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800225} drm_r128_fullscreen_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700226#define R128_PARAM_IRQ_NR 1
227typedef struct drm_r128_getparam {
Tao Baod7db5942015-01-28 10:07:51 -0800228 int param;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800229 void __user * value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700230} drm_r128_getparam_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700231#ifdef __cplusplus
232#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700233#endif