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gerrit.omnirom.org / android_bionic / 40854235256c3f51f9ea866f5f8ef03240c00123 / . / libc / kernel / uapi / rdma / mlx5-abi.h
blob: 7b2badd9998ecc3668fd45e70f5c8f2882831706 [file] [log] [blame]
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef MLX5_ABI_USER_H
20#define MLX5_ABI_USER_H
21#include <linux/types.h>
22enum {
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
25 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
26};
27enum {
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
30};
31enum {
32 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34};
35#define MLX5_IB_UVERBS_ABI_VERSION 1
36struct mlx5_ib_alloc_ucontext_req {
37 __u32 total_num_uuars;
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39 __u32 num_low_latency_uuars;
40};
41struct mlx5_ib_alloc_ucontext_req_v2 {
42 __u32 total_num_uuars;
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44 __u32 num_low_latency_uuars;
45 __u32 flags;
46 __u32 comp_mask;
47 __u8 max_cqe_version;
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49 __u8 reserved0;
50 __u16 reserved1;
51 __u32 reserved2;
52};
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54enum mlx5_ib_alloc_ucontext_resp_mask {
55 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
56};
57enum mlx5_user_cmds_supp_uhw {
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
60};
61struct mlx5_ib_alloc_ucontext_resp {
62 __u32 qp_tab_size;
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64 __u32 bf_reg_size;
65 __u32 tot_uuars;
66 __u32 cache_line_size;
67 __u16 max_sq_desc_sz;
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69 __u16 max_rq_desc_sz;
70 __u32 max_send_wqebb;
71 __u32 max_recv_wr;
72 __u32 max_srq_recv_wr;
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74 __u16 num_ports;
75 __u16 reserved1;
76 __u32 comp_mask;
77 __u32 response_length;
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79 __u8 cqe_version;
80 __u8 cmds_supp_uhw;
81 __u16 reserved2;
82 __u64 hca_core_clock_offset;
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84};
85struct mlx5_ib_alloc_pd_resp {
86 __u32 pdn;
87};
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89struct mlx5_ib_tso_caps {
90 __u32 max_tso;
91 __u32 supported_qpts;
92};
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94struct mlx5_ib_rss_caps {
95 __u64 rx_hash_fields_mask;
96 __u8 rx_hash_function;
97 __u8 reserved[7];
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99};
100struct mlx5_ib_query_device_resp {
101 __u32 comp_mask;
102 __u32 response_length;
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104 struct mlx5_ib_tso_caps tso_caps;
105 struct mlx5_ib_rss_caps rss_caps;
106};
107struct mlx5_ib_create_cq {
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109 __u64 buf_addr;
110 __u64 db_addr;
111 __u32 cqe_size;
112 __u32 reserved;
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114};
115struct mlx5_ib_create_cq_resp {
116 __u32 cqn;
117 __u32 reserved;
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119};
120struct mlx5_ib_resize_cq {
121 __u64 buf_addr;
122 __u16 cqe_size;
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124 __u16 reserved0;
125 __u32 reserved1;
126};
127struct mlx5_ib_create_srq {
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129 __u64 buf_addr;
130 __u64 db_addr;
131 __u32 flags;
132 __u32 reserved0;
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134 __u32 uidx;
135 __u32 reserved1;
136};
137struct mlx5_ib_create_srq_resp {
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139 __u32 srqn;
140 __u32 reserved;
141};
142struct mlx5_ib_create_qp {
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144 __u64 buf_addr;
145 __u64 db_addr;
146 __u32 sq_wqe_count;
147 __u32 rq_wqe_count;
148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
149 __u32 rq_wqe_shift;
150 __u32 flags;
151 __u32 uidx;
152 __u32 reserved0;
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
154 __u64 sq_buf_addr;
155};
156enum mlx5_rx_hash_function_flags {
157 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
159};
160enum mlx5_rx_hash_fields {
161 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
162 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
164 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
165 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
166 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
167 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
169 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
170 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
171};
172struct mlx5_ib_create_qp_rss {
173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
174 __u64 rx_hash_fields_mask;
175 __u8 rx_hash_function;
176 __u8 rx_key_len;
177 __u8 reserved[6];
178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
179 __u8 rx_hash_key[128];
180 __u32 comp_mask;
181 __u32 reserved1;
182};
183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
184struct mlx5_ib_create_qp_resp {
185 __u32 uuar_index;
186};
187struct mlx5_ib_alloc_mw {
188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
189 __u32 comp_mask;
190 __u8 num_klms;
191 __u8 reserved1;
192 __u16 reserved2;
193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
194};
195struct mlx5_ib_create_wq {
196 __u64 buf_addr;
197 __u64 db_addr;
198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
199 __u32 rq_wqe_count;
200 __u32 rq_wqe_shift;
201 __u32 user_index;
202 __u32 flags;
203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
204 __u32 comp_mask;
205 __u32 reserved;
206};
207struct mlx5_ib_create_wq_resp {
208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
209 __u32 response_length;
210 __u32 reserved;
211};
212struct mlx5_ib_create_rwq_ind_tbl_resp {
213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
214 __u32 response_length;
215 __u32 reserved;
216};
217struct mlx5_ib_modify_wq {
218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
219 __u32 comp_mask;
220 __u32 reserved;
221};
222#endif
223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */