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Christopher Ferris6a9755d2017-01-13 14:09:31 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef MLX5_ABI_USER_H
20#define MLX5_ABI_USER_H
21#include <linux/types.h>
Christopher Ferris525ce912017-07-26 13:12:53 -070022#include <linux/if_ether.h>
Christopher Ferris9ce28842018-10-25 12:11:39 -070023#include <rdma/ib_user_ioctl_verbs.h>
Christopher Ferris6a9755d2017-01-13 14:09:31 -080024enum {
Christopher Ferris6a9755d2017-01-13 14:09:31 -080025 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
26 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
Christopher Ferris934ec942018-01-31 15:29:16 -080027 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
Christopher Ferris76a1d452018-06-27 14:12:29 -070028 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
29 MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
30 MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
Christopher Ferris86a48372019-01-10 14:14:59 -080031 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
32 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
33 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
Christopher Ferrisd842e432019-03-07 10:21:59 -080034 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9,
Christopher Ferrisaf09c702020-06-01 20:29:29 -070035 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080036};
37enum {
Christopher Ferris6a9755d2017-01-13 14:09:31 -080038 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
39};
40enum {
41 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080042};
43#define MLX5_IB_UVERBS_ABI_VERSION 1
44struct mlx5_ib_alloc_ucontext_req {
Christopher Ferris525ce912017-07-26 13:12:53 -070045 __u32 total_num_bfregs;
46 __u32 num_low_latency_bfregs;
47};
48enum mlx5_lib_caps {
49 MLX5_LIB_CAP_4K_UAR = (__u64) 1 << 0,
Christopher Ferrisaf09c702020-06-01 20:29:29 -070050 MLX5_LIB_CAP_DYN_UAR = (__u64) 1 << 1,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080051};
Christopher Ferris9ce28842018-10-25 12:11:39 -070052enum mlx5_ib_alloc_uctx_v2_flags {
53 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0,
54};
Christopher Ferris6a9755d2017-01-13 14:09:31 -080055struct mlx5_ib_alloc_ucontext_req_v2 {
Christopher Ferris525ce912017-07-26 13:12:53 -070056 __u32 total_num_bfregs;
57 __u32 num_low_latency_bfregs;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080058 __u32 flags;
59 __u32 comp_mask;
60 __u8 max_cqe_version;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080061 __u8 reserved0;
62 __u16 reserved1;
63 __u32 reserved2;
Christopher Ferris76a1d452018-06-27 14:12:29 -070064 __aligned_u64 lib_caps;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080065};
Christopher Ferris6a9755d2017-01-13 14:09:31 -080066enum mlx5_ib_alloc_ucontext_resp_mask {
67 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
Christopher Ferris9ce28842018-10-25 12:11:39 -070068 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
Christopher Ferris8177cdf2020-08-03 11:53:55 -070069 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
Christopher Ferris3a39c0b2021-09-02 00:03:38 +000070 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3,
71 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080072};
73enum mlx5_user_cmds_supp_uhw {
Christopher Ferris6a9755d2017-01-13 14:09:31 -080074 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080075 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
Christopher Ferris6a9755d2017-01-13 14:09:31 -080076};
Christopher Ferris525ce912017-07-26 13:12:53 -070077enum mlx5_user_inline_mode {
78 MLX5_USER_INLINE_MODE_NA,
79 MLX5_USER_INLINE_MODE_NONE,
80 MLX5_USER_INLINE_MODE_L2,
81 MLX5_USER_INLINE_MODE_IP,
82 MLX5_USER_INLINE_MODE_TCP_UDP,
83};
Christopher Ferris76a1d452018-06-27 14:12:29 -070084enum {
85 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
86 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
87 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
88 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
89 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
90};
Christopher Ferris6a9755d2017-01-13 14:09:31 -080091struct mlx5_ib_alloc_ucontext_resp {
Christopher Ferris48af7cb2017-02-21 12:35:09 -080092 __u32 qp_tab_size;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080093 __u32 bf_reg_size;
Christopher Ferris525ce912017-07-26 13:12:53 -070094 __u32 tot_bfregs;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080095 __u32 cache_line_size;
Christopher Ferris48af7cb2017-02-21 12:35:09 -080096 __u16 max_sq_desc_sz;
Christopher Ferris6a9755d2017-01-13 14:09:31 -080097 __u16 max_rq_desc_sz;
98 __u32 max_send_wqebb;
99 __u32 max_recv_wr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800100 __u32 max_srq_recv_wr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800101 __u16 num_ports;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700102 __u16 flow_action_flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800103 __u32 comp_mask;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800104 __u32 response_length;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800105 __u8 cqe_version;
106 __u8 cmds_supp_uhw;
Christopher Ferris525ce912017-07-26 13:12:53 -0700107 __u8 eth_min_inline;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700108 __u8 clock_info_versions;
109 __aligned_u64 hca_core_clock_offset;
Christopher Ferris525ce912017-07-26 13:12:53 -0700110 __u32 log_uar_size;
111 __u32 num_uars_per_page;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700112 __u32 num_dyn_bfregs;
Christopher Ferris9ce28842018-10-25 12:11:39 -0700113 __u32 dump_fill_mkey;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800114};
115struct mlx5_ib_alloc_pd_resp {
116 __u32 pdn;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800117};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800118struct mlx5_ib_tso_caps {
119 __u32 max_tso;
120 __u32 supported_qpts;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800121};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800122struct mlx5_ib_rss_caps {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700123 __aligned_u64 rx_hash_fields_mask;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800124 __u8 rx_hash_function;
125 __u8 reserved[7];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800126};
127enum mlx5_ib_cqe_comp_res_format {
128 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800129 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
Christopher Ferris9ce28842018-10-25 12:11:39 -0700130 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800131};
132struct mlx5_ib_cqe_comp_caps {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800133 __u32 max_num;
134 __u32 supported_format;
135};
Christopher Ferris76a1d452018-06-27 14:12:29 -0700136enum mlx5_ib_packet_pacing_cap_flags {
137 MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
138};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800139struct mlx5_packet_pacing_caps {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800140 __u32 qp_rate_limit_min;
141 __u32 qp_rate_limit_max;
142 __u32 supported_qpts;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700143 __u8 cap_flags;
144 __u8 reserved[3];
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800145};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800146enum mlx5_ib_mpw_caps {
147 MPW_RESERVED = 1 << 0,
148 MLX5_IB_ALLOW_MPW = 1 << 1,
149 MLX5_IB_SUPPORT_EMPW = 1 << 2,
150};
151enum mlx5_ib_sw_parsing_offloads {
152 MLX5_IB_SW_PARSING = 1 << 0,
153 MLX5_IB_SW_PARSING_CSUM = 1 << 1,
154 MLX5_IB_SW_PARSING_LSO = 1 << 2,
155};
156struct mlx5_ib_sw_parsing_caps {
157 __u32 sw_parsing_offloads;
158 __u32 supported_qpts;
159};
Christopher Ferris934ec942018-01-31 15:29:16 -0800160struct mlx5_ib_striding_rq_caps {
161 __u32 min_single_stride_log_num_of_bytes;
162 __u32 max_single_stride_log_num_of_bytes;
163 __u32 min_single_wqe_log_num_of_strides;
164 __u32 max_single_wqe_log_num_of_strides;
165 __u32 supported_qpts;
166 __u32 reserved;
167};
168enum mlx5_ib_query_dev_resp_flags {
169 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
170 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
Christopher Ferrisd842e432019-03-07 10:21:59 -0800171 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700172 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
Christopher Ferris934ec942018-01-31 15:29:16 -0800173};
174enum mlx5_ib_tunnel_offloads {
175 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
176 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
Christopher Ferris9ce28842018-10-25 12:11:39 -0700177 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
178 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
179 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
Christopher Ferris934ec942018-01-31 15:29:16 -0800180};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800181struct mlx5_ib_query_device_resp {
182 __u32 comp_mask;
183 __u32 response_length;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800184 struct mlx5_ib_tso_caps tso_caps;
185 struct mlx5_ib_rss_caps rss_caps;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800186 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
187 struct mlx5_packet_pacing_caps packet_pacing_caps;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800188 __u32 mlx5_ib_support_multi_pkt_send_wqes;
Christopher Ferris934ec942018-01-31 15:29:16 -0800189 __u32 flags;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800190 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
Christopher Ferris934ec942018-01-31 15:29:16 -0800191 struct mlx5_ib_striding_rq_caps striding_rq_caps;
192 __u32 tunnel_offloads_caps;
193 __u32 reserved;
194};
195enum mlx5_ib_create_cq_flags {
196 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
Christopher Ferrisaf09c702020-06-01 20:29:29 -0700197 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1,
Christopher Ferris3a39c0b2021-09-02 00:03:38 +0000198 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS = 1 << 2,
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800199};
200struct mlx5_ib_create_cq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700201 __aligned_u64 buf_addr;
202 __aligned_u64 db_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800203 __u32 cqe_size;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800204 __u8 cqe_comp_en;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800205 __u8 cqe_comp_res_format;
Christopher Ferris934ec942018-01-31 15:29:16 -0800206 __u16 flags;
Christopher Ferrisaf09c702020-06-01 20:29:29 -0700207 __u16 uar_page_index;
208 __u16 reserved0;
209 __u32 reserved1;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800210};
211struct mlx5_ib_create_cq_resp {
212 __u32 cqn;
213 __u32 reserved;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800214};
215struct mlx5_ib_resize_cq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700216 __aligned_u64 buf_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800217 __u16 cqe_size;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800218 __u16 reserved0;
219 __u32 reserved1;
220};
221struct mlx5_ib_create_srq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700222 __aligned_u64 buf_addr;
223 __aligned_u64 db_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800224 __u32 flags;
225 __u32 reserved0;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800226 __u32 uidx;
227 __u32 reserved1;
228};
229struct mlx5_ib_create_srq_resp {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800230 __u32 srqn;
231 __u32 reserved;
232};
233struct mlx5_ib_create_qp {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700234 __aligned_u64 buf_addr;
235 __aligned_u64 db_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800236 __u32 sq_wqe_count;
237 __u32 rq_wqe_count;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800238 __u32 rq_wqe_shift;
239 __u32 flags;
240 __u32 uidx;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700241 __u32 bfreg_index;
242 union {
243 __aligned_u64 sq_buf_addr;
244 __aligned_u64 access_key;
245 };
Christopher Ferris8177cdf2020-08-03 11:53:55 -0700246 __u32 ece_options;
247 __u32 reserved;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800248};
249enum mlx5_rx_hash_function_flags {
250 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800251};
252enum mlx5_rx_hash_fields {
253 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
254 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800255 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
256 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
257 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
258 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800259 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
Christopher Ferris934ec942018-01-31 15:29:16 -0800260 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
Christopher Ferris76a1d452018-06-27 14:12:29 -0700261 MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
262 MLX5_RX_HASH_INNER = (1UL << 31),
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800263};
264struct mlx5_ib_create_qp_rss {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700265 __aligned_u64 rx_hash_fields_mask;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800266 __u8 rx_hash_function;
267 __u8 rx_key_len;
268 __u8 reserved[6];
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800269 __u8 rx_hash_key[128];
270 __u32 comp_mask;
Christopher Ferris934ec942018-01-31 15:29:16 -0800271 __u32 flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800272};
Christopher Ferris86a48372019-01-10 14:14:59 -0800273enum mlx5_ib_create_qp_resp_mask {
274 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
275 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
276 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2,
277 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3,
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700278 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4,
Christopher Ferris86a48372019-01-10 14:14:59 -0800279};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800280struct mlx5_ib_create_qp_resp {
Christopher Ferris525ce912017-07-26 13:12:53 -0700281 __u32 bfreg_index;
Christopher Ferris8177cdf2020-08-03 11:53:55 -0700282 __u32 ece_options;
Christopher Ferris86a48372019-01-10 14:14:59 -0800283 __u32 comp_mask;
284 __u32 tirn;
285 __u32 tisn;
286 __u32 rqn;
287 __u32 sqn;
288 __u32 reserved1;
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700289 __u64 tir_icm_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800290};
291struct mlx5_ib_alloc_mw {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800292 __u32 comp_mask;
293 __u8 num_klms;
294 __u8 reserved1;
295 __u16 reserved2;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800296};
Christopher Ferris934ec942018-01-31 15:29:16 -0800297enum mlx5_ib_create_wq_mask {
298 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
299};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800300struct mlx5_ib_create_wq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700301 __aligned_u64 buf_addr;
302 __aligned_u64 db_addr;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800303 __u32 rq_wqe_count;
304 __u32 rq_wqe_shift;
305 __u32 user_index;
306 __u32 flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800307 __u32 comp_mask;
Christopher Ferris934ec942018-01-31 15:29:16 -0800308 __u32 single_stride_log_num_of_bytes;
309 __u32 single_wqe_log_num_of_strides;
310 __u32 two_byte_shift_en;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800311};
312struct mlx5_ib_create_ah_resp {
313 __u32 response_length;
314 __u8 dmac[ETH_ALEN];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800315 __u8 reserved[6];
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800316};
Christopher Ferris76a1d452018-06-27 14:12:29 -0700317struct mlx5_ib_burst_info {
318 __u32 max_burst_sz;
319 __u16 typical_pkt_sz;
320 __u16 reserved;
321};
322struct mlx5_ib_modify_qp {
323 __u32 comp_mask;
324 struct mlx5_ib_burst_info burst_info;
Christopher Ferris8177cdf2020-08-03 11:53:55 -0700325 __u32 ece_options;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700326};
327struct mlx5_ib_modify_qp_resp {
328 __u32 response_length;
329 __u32 dctn;
Christopher Ferris8177cdf2020-08-03 11:53:55 -0700330 __u32 ece_options;
331 __u32 reserved;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700332};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800333struct mlx5_ib_create_wq_resp {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800334 __u32 response_length;
335 __u32 reserved;
336};
337struct mlx5_ib_create_rwq_ind_tbl_resp {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800338 __u32 response_length;
339 __u32 reserved;
340};
341struct mlx5_ib_modify_wq {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800342 __u32 comp_mask;
343 __u32 reserved;
344};
Christopher Ferris76a1d452018-06-27 14:12:29 -0700345struct mlx5_ib_clock_info {
346 __u32 sign;
347 __u32 resv;
348 __aligned_u64 nsec;
349 __aligned_u64 cycles;
350 __aligned_u64 frac;
351 __u32 mult;
352 __u32 shift;
353 __aligned_u64 mask;
354 __aligned_u64 overflow_period;
355};
356enum mlx5_ib_mmap_cmd {
357 MLX5_IB_MMAP_REGULAR_PAGE = 0,
358 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
359 MLX5_IB_MMAP_WC_PAGE = 2,
360 MLX5_IB_MMAP_NC_PAGE = 3,
361 MLX5_IB_MMAP_CORE_CLOCK = 5,
362 MLX5_IB_MMAP_ALLOC_WC = 6,
363 MLX5_IB_MMAP_CLOCK_INFO = 7,
364 MLX5_IB_MMAP_DEVICE_MEM = 8,
365};
366enum {
367 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
368};
369enum {
370 MLX5_IB_CLOCK_INFO_V1 = 0,
371};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700372struct mlx5_ib_flow_counters_desc {
373 __u32 description;
374 __u32 index;
375};
376struct mlx5_ib_flow_counters_data {
377 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
378 __u32 ncounters;
379 __u32 reserved;
380};
381struct mlx5_ib_create_flow {
382 __u32 ncounters_data;
383 __u32 reserved;
384 struct mlx5_ib_flow_counters_data data[];
385};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800386#endif