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gerrit.omnirom.org / android_bionic / 0b27d314d6d7e66427af7354c05919a0ca8be6bc / . / libc / kernel / uapi / drm / qaic_accel.h
blob: d2a43cfa5bab6cb946de16954e6472c2675eb5e5 [file] [log] [blame]
Christopher Ferris37c3f3c2023-07-10 10:59:05 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef QAIC_ACCEL_H_
20#define QAIC_ACCEL_H_
21#include "drm.h"
22#ifdef __cplusplus
23extern "C" {
24#endif
25#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K
26#define QAIC_SEM_INSYNCFENCE 2
27#define QAIC_SEM_OUTSYNCFENCE 1
28#define QAIC_SEM_NOP 0
29#define QAIC_SEM_INIT 1
30#define QAIC_SEM_INC 2
31#define QAIC_SEM_DEC 3
32#define QAIC_SEM_WAIT_EQUAL 4
33#define QAIC_SEM_WAIT_GT_EQ 5
34#define QAIC_SEM_WAIT_GT_0 6
35#define QAIC_TRANS_UNDEFINED 0
36#define QAIC_TRANS_PASSTHROUGH_FROM_USR 1
37#define QAIC_TRANS_PASSTHROUGH_TO_USR 2
38#define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3
39#define QAIC_TRANS_PASSTHROUGH_TO_DEV 4
40#define QAIC_TRANS_DMA_XFER_FROM_USR 5
41#define QAIC_TRANS_DMA_XFER_TO_DEV 6
42#define QAIC_TRANS_ACTIVATE_FROM_USR 7
43#define QAIC_TRANS_ACTIVATE_FROM_DEV 8
44#define QAIC_TRANS_ACTIVATE_TO_DEV 9
45#define QAIC_TRANS_DEACTIVATE_FROM_USR 10
46#define QAIC_TRANS_DEACTIVATE_FROM_DEV 11
47#define QAIC_TRANS_STATUS_FROM_USR 12
48#define QAIC_TRANS_STATUS_TO_USR 13
49#define QAIC_TRANS_STATUS_FROM_DEV 14
50#define QAIC_TRANS_STATUS_TO_DEV 15
51#define QAIC_TRANS_TERMINATE_FROM_DEV 16
52#define QAIC_TRANS_TERMINATE_TO_DEV 17
53#define QAIC_TRANS_DMA_XFER_CONT 18
54#define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19
55#define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20
56struct qaic_manage_trans_hdr {
57 __u32 type;
58 __u32 len;
59};
60struct qaic_manage_trans_passthrough {
61 struct qaic_manage_trans_hdr hdr;
62 __u8 data[];
63};
64struct qaic_manage_trans_dma_xfer {
65 struct qaic_manage_trans_hdr hdr;
66 __u32 tag;
67 __u32 pad;
68 __u64 addr;
69 __u64 size;
70};
71struct qaic_manage_trans_activate_to_dev {
72 struct qaic_manage_trans_hdr hdr;
73 __u32 queue_size;
74 __u32 eventfd;
75 __u32 options;
76 __u32 pad;
77};
78struct qaic_manage_trans_activate_from_dev {
79 struct qaic_manage_trans_hdr hdr;
80 __u32 status;
81 __u32 dbc_id;
82 __u64 options;
83};
84struct qaic_manage_trans_deactivate {
85 struct qaic_manage_trans_hdr hdr;
86 __u32 dbc_id;
87 __u32 pad;
88};
89struct qaic_manage_trans_status_to_dev {
90 struct qaic_manage_trans_hdr hdr;
91};
92struct qaic_manage_trans_status_from_dev {
93 struct qaic_manage_trans_hdr hdr;
94 __u16 major;
95 __u16 minor;
96 __u32 status;
97 __u64 status_flags;
98};
99struct qaic_manage_msg {
100 __u32 len;
101 __u32 count;
102 __u64 data;
103};
104struct qaic_create_bo {
105 __u64 size;
106 __u32 handle;
107 __u32 pad;
108};
109struct qaic_mmap_bo {
110 __u32 handle;
111 __u32 pad;
112 __u64 offset;
113};
114struct qaic_sem {
115 __u16 val;
116 __u8 index;
117 __u8 presync;
118 __u8 cmd;
119 __u8 flags;
120 __u16 pad;
121};
122struct qaic_attach_slice_entry {
123 __u64 size;
124 struct qaic_sem sem0;
125 struct qaic_sem sem1;
126 struct qaic_sem sem2;
127 struct qaic_sem sem3;
128 __u64 dev_addr;
129 __u64 db_addr;
130 __u32 db_data;
131 __u32 db_len;
132 __u64 offset;
133};
134struct qaic_attach_slice_hdr {
135 __u32 count;
136 __u32 dbc_id;
137 __u32 handle;
138 __u32 dir;
139 __u64 size;
140};
141struct qaic_attach_slice {
142 struct qaic_attach_slice_hdr hdr;
143 __u64 data;
144};
145struct qaic_execute_entry {
146 __u32 handle;
147 __u32 dir;
148};
149struct qaic_partial_execute_entry {
150 __u32 handle;
151 __u32 dir;
152 __u64 resize;
153};
154struct qaic_execute_hdr {
155 __u32 count;
156 __u32 dbc_id;
157};
158struct qaic_execute {
159 struct qaic_execute_hdr hdr;
160 __u64 data;
161};
162struct qaic_wait {
163 __u32 handle;
164 __u32 timeout;
165 __u32 dbc_id;
166 __u32 pad;
167};
168struct qaic_perf_stats_hdr {
169 __u16 count;
170 __u16 pad;
171 __u32 dbc_id;
172};
173struct qaic_perf_stats {
174 struct qaic_perf_stats_hdr hdr;
175 __u64 data;
176};
177struct qaic_perf_stats_entry {
178 __u32 handle;
179 __u32 queue_level_before;
180 __u32 num_queue_element;
181 __u32 submit_latency_us;
182 __u32 device_latency_us;
183 __u32 pad;
184};
185#define DRM_QAIC_MANAGE 0x00
186#define DRM_QAIC_CREATE_BO 0x01
187#define DRM_QAIC_MMAP_BO 0x02
188#define DRM_QAIC_ATTACH_SLICE_BO 0x03
189#define DRM_QAIC_EXECUTE_BO 0x04
190#define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05
191#define DRM_QAIC_WAIT_BO 0x06
192#define DRM_QAIC_PERF_STATS_BO 0x07
193#define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg)
194#define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo)
195#define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo)
196#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice)
197#define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute)
198#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute)
199#define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait)
200#define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats)
201#ifdef __cplusplus
202}
203#endif
204#endif