blob: 387e3f136052dbcaa5142b0e2d36bc23d5c38f34 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DVBFRONTEND_H_
20#define _DVBFRONTEND_H_
21#include <linux/types.h>
Christopher Ferris05d08e92016-02-04 13:16:38 -080022enum fe_type {
Tao Baod7db5942015-01-28 10:07:51 -080023 FE_QPSK,
24 FE_QAM,
25 FE_OFDM,
26 FE_ATSC
Christopher Ferris05d08e92016-02-04 13:16:38 -080027};
28enum fe_caps {
Tao Baod7db5942015-01-28 10:07:51 -080029 FE_IS_STUPID = 0,
30 FE_CAN_INVERSION_AUTO = 0x1,
Tao Baod7db5942015-01-28 10:07:51 -080031 FE_CAN_FEC_1_2 = 0x2,
32 FE_CAN_FEC_2_3 = 0x4,
33 FE_CAN_FEC_3_4 = 0x8,
34 FE_CAN_FEC_4_5 = 0x10,
Tao Baod7db5942015-01-28 10:07:51 -080035 FE_CAN_FEC_5_6 = 0x20,
36 FE_CAN_FEC_6_7 = 0x40,
37 FE_CAN_FEC_7_8 = 0x80,
38 FE_CAN_FEC_8_9 = 0x100,
Tao Baod7db5942015-01-28 10:07:51 -080039 FE_CAN_FEC_AUTO = 0x200,
40 FE_CAN_QPSK = 0x400,
41 FE_CAN_QAM_16 = 0x800,
42 FE_CAN_QAM_32 = 0x1000,
Tao Baod7db5942015-01-28 10:07:51 -080043 FE_CAN_QAM_64 = 0x2000,
44 FE_CAN_QAM_128 = 0x4000,
45 FE_CAN_QAM_256 = 0x8000,
46 FE_CAN_QAM_AUTO = 0x10000,
Tao Baod7db5942015-01-28 10:07:51 -080047 FE_CAN_TRANSMISSION_MODE_AUTO = 0x20000,
48 FE_CAN_BANDWIDTH_AUTO = 0x40000,
49 FE_CAN_GUARD_INTERVAL_AUTO = 0x80000,
50 FE_CAN_HIERARCHY_AUTO = 0x100000,
Tao Baod7db5942015-01-28 10:07:51 -080051 FE_CAN_8VSB = 0x200000,
52 FE_CAN_16VSB = 0x400000,
53 FE_HAS_EXTENDED_CAPS = 0x800000,
54 FE_CAN_MULTISTREAM = 0x4000000,
Tao Baod7db5942015-01-28 10:07:51 -080055 FE_CAN_TURBO_FEC = 0x8000000,
56 FE_CAN_2G_MODULATION = 0x10000000,
57 FE_NEEDS_BENDING = 0x20000000,
58 FE_CAN_RECOVER = 0x40000000,
Tao Baod7db5942015-01-28 10:07:51 -080059 FE_CAN_MUTE_TS = 0x80000000
Christopher Ferris05d08e92016-02-04 13:16:38 -080060};
Ben Cheng655a7c02013-10-16 16:09:24 -070061struct dvb_frontend_info {
Tao Baod7db5942015-01-28 10:07:51 -080062 char name[128];
Christopher Ferris05d08e92016-02-04 13:16:38 -080063 enum fe_type type;
Tao Baod7db5942015-01-28 10:07:51 -080064 __u32 frequency_min;
65 __u32 frequency_max;
66 __u32 frequency_stepsize;
Tao Baod7db5942015-01-28 10:07:51 -080067 __u32 frequency_tolerance;
68 __u32 symbol_rate_min;
69 __u32 symbol_rate_max;
70 __u32 symbol_rate_tolerance;
Tao Baod7db5942015-01-28 10:07:51 -080071 __u32 notifier_delay;
Christopher Ferris05d08e92016-02-04 13:16:38 -080072 enum fe_caps caps;
Ben Cheng655a7c02013-10-16 16:09:24 -070073};
74struct dvb_diseqc_master_cmd {
Tao Baod7db5942015-01-28 10:07:51 -080075 __u8 msg[6];
76 __u8 msg_len;
Ben Cheng655a7c02013-10-16 16:09:24 -070077};
78struct dvb_diseqc_slave_reply {
Tao Baod7db5942015-01-28 10:07:51 -080079 __u8 msg[4];
80 __u8 msg_len;
81 int timeout;
Ben Cheng655a7c02013-10-16 16:09:24 -070082};
Christopher Ferris05d08e92016-02-04 13:16:38 -080083enum fe_sec_voltage {
Tao Baod7db5942015-01-28 10:07:51 -080084 SEC_VOLTAGE_13,
85 SEC_VOLTAGE_18,
86 SEC_VOLTAGE_OFF
Christopher Ferris05d08e92016-02-04 13:16:38 -080087};
88enum fe_sec_tone_mode {
Tao Baod7db5942015-01-28 10:07:51 -080089 SEC_TONE_ON,
90 SEC_TONE_OFF
Christopher Ferris05d08e92016-02-04 13:16:38 -080091};
92enum fe_sec_mini_cmd {
Tao Baod7db5942015-01-28 10:07:51 -080093 SEC_MINI_A,
94 SEC_MINI_B
Christopher Ferris05d08e92016-02-04 13:16:38 -080095};
96enum fe_status {
Tao Baod7db5942015-01-28 10:07:51 -080097 FE_HAS_SIGNAL = 0x01,
98 FE_HAS_CARRIER = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -080099 FE_HAS_VITERBI = 0x04,
100 FE_HAS_SYNC = 0x08,
101 FE_HAS_LOCK = 0x10,
102 FE_TIMEDOUT = 0x20,
Tao Baod7db5942015-01-28 10:07:51 -0800103 FE_REINIT = 0x40,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800104};
105enum fe_spectral_inversion {
Tao Baod7db5942015-01-28 10:07:51 -0800106 INVERSION_OFF,
Tao Baod7db5942015-01-28 10:07:51 -0800107 INVERSION_ON,
108 INVERSION_AUTO
Christopher Ferris05d08e92016-02-04 13:16:38 -0800109};
110enum fe_code_rate {
Tao Baod7db5942015-01-28 10:07:51 -0800111 FEC_NONE = 0,
112 FEC_1_2,
113 FEC_2_3,
114 FEC_3_4,
Tao Baod7db5942015-01-28 10:07:51 -0800115 FEC_4_5,
116 FEC_5_6,
117 FEC_6_7,
118 FEC_7_8,
Tao Baod7db5942015-01-28 10:07:51 -0800119 FEC_8_9,
120 FEC_AUTO,
121 FEC_3_5,
122 FEC_9_10,
Tao Baod7db5942015-01-28 10:07:51 -0800123 FEC_2_5,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800124};
125enum fe_modulation {
Tao Baod7db5942015-01-28 10:07:51 -0800126 QPSK,
Tao Baod7db5942015-01-28 10:07:51 -0800127 QAM_16,
128 QAM_32,
129 QAM_64,
130 QAM_128,
Tao Baod7db5942015-01-28 10:07:51 -0800131 QAM_256,
132 QAM_AUTO,
133 VSB_8,
134 VSB_16,
Tao Baod7db5942015-01-28 10:07:51 -0800135 PSK_8,
136 APSK_16,
137 APSK_32,
138 DQPSK,
Tao Baod7db5942015-01-28 10:07:51 -0800139 QAM_4_NR,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800140};
141enum fe_transmit_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800142 TRANSMISSION_MODE_2K,
Tao Baod7db5942015-01-28 10:07:51 -0800143 TRANSMISSION_MODE_8K,
144 TRANSMISSION_MODE_AUTO,
145 TRANSMISSION_MODE_4K,
146 TRANSMISSION_MODE_1K,
Tao Baod7db5942015-01-28 10:07:51 -0800147 TRANSMISSION_MODE_16K,
148 TRANSMISSION_MODE_32K,
149 TRANSMISSION_MODE_C1,
150 TRANSMISSION_MODE_C3780,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800151};
152enum fe_guard_interval {
Tao Baod7db5942015-01-28 10:07:51 -0800153 GUARD_INTERVAL_1_32,
Tao Baod7db5942015-01-28 10:07:51 -0800154 GUARD_INTERVAL_1_16,
155 GUARD_INTERVAL_1_8,
156 GUARD_INTERVAL_1_4,
157 GUARD_INTERVAL_AUTO,
Tao Baod7db5942015-01-28 10:07:51 -0800158 GUARD_INTERVAL_1_128,
159 GUARD_INTERVAL_19_128,
160 GUARD_INTERVAL_19_256,
161 GUARD_INTERVAL_PN420,
Tao Baod7db5942015-01-28 10:07:51 -0800162 GUARD_INTERVAL_PN595,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800163 GUARD_INTERVAL_PN945,
164};
165enum fe_hierarchy {
Tao Baod7db5942015-01-28 10:07:51 -0800166 HIERARCHY_NONE,
167 HIERARCHY_1,
168 HIERARCHY_2,
169 HIERARCHY_4,
Tao Baod7db5942015-01-28 10:07:51 -0800170 HIERARCHY_AUTO
Christopher Ferris05d08e92016-02-04 13:16:38 -0800171};
Ben Cheng655a7c02013-10-16 16:09:24 -0700172enum fe_interleaving {
Tao Baod7db5942015-01-28 10:07:51 -0800173 INTERLEAVING_NONE,
Tao Baod7db5942015-01-28 10:07:51 -0800174 INTERLEAVING_AUTO,
175 INTERLEAVING_240,
176 INTERLEAVING_720,
Ben Cheng655a7c02013-10-16 16:09:24 -0700177};
Ben Cheng655a7c02013-10-16 16:09:24 -0700178#define DTV_UNDEFINED 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700179#define DTV_TUNE 1
180#define DTV_CLEAR 2
181#define DTV_FREQUENCY 3
182#define DTV_MODULATION 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700183#define DTV_BANDWIDTH_HZ 5
184#define DTV_INVERSION 6
185#define DTV_DISEQC_MASTER 7
186#define DTV_SYMBOL_RATE 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700187#define DTV_INNER_FEC 9
188#define DTV_VOLTAGE 10
189#define DTV_TONE 11
190#define DTV_PILOT 12
Ben Cheng655a7c02013-10-16 16:09:24 -0700191#define DTV_ROLLOFF 13
192#define DTV_DISEQC_SLAVE_REPLY 14
193#define DTV_FE_CAPABILITY_COUNT 15
194#define DTV_FE_CAPABILITY 16
Ben Cheng655a7c02013-10-16 16:09:24 -0700195#define DTV_DELIVERY_SYSTEM 17
196#define DTV_ISDBT_PARTIAL_RECEPTION 18
197#define DTV_ISDBT_SOUND_BROADCASTING 19
198#define DTV_ISDBT_SB_SUBCHANNEL_ID 20
Ben Cheng655a7c02013-10-16 16:09:24 -0700199#define DTV_ISDBT_SB_SEGMENT_IDX 21
200#define DTV_ISDBT_SB_SEGMENT_COUNT 22
201#define DTV_ISDBT_LAYERA_FEC 23
202#define DTV_ISDBT_LAYERA_MODULATION 24
Ben Cheng655a7c02013-10-16 16:09:24 -0700203#define DTV_ISDBT_LAYERA_SEGMENT_COUNT 25
204#define DTV_ISDBT_LAYERA_TIME_INTERLEAVING 26
205#define DTV_ISDBT_LAYERB_FEC 27
206#define DTV_ISDBT_LAYERB_MODULATION 28
Ben Cheng655a7c02013-10-16 16:09:24 -0700207#define DTV_ISDBT_LAYERB_SEGMENT_COUNT 29
208#define DTV_ISDBT_LAYERB_TIME_INTERLEAVING 30
209#define DTV_ISDBT_LAYERC_FEC 31
210#define DTV_ISDBT_LAYERC_MODULATION 32
Ben Cheng655a7c02013-10-16 16:09:24 -0700211#define DTV_ISDBT_LAYERC_SEGMENT_COUNT 33
212#define DTV_ISDBT_LAYERC_TIME_INTERLEAVING 34
213#define DTV_API_VERSION 35
214#define DTV_CODE_RATE_HP 36
Ben Cheng655a7c02013-10-16 16:09:24 -0700215#define DTV_CODE_RATE_LP 37
216#define DTV_GUARD_INTERVAL 38
217#define DTV_TRANSMISSION_MODE 39
218#define DTV_HIERARCHY 40
Ben Cheng655a7c02013-10-16 16:09:24 -0700219#define DTV_ISDBT_LAYER_ENABLED 41
220#define DTV_STREAM_ID 42
221#define DTV_ISDBS_TS_ID_LEGACY DTV_STREAM_ID
222#define DTV_DVBT2_PLP_ID_LEGACY 43
Ben Cheng655a7c02013-10-16 16:09:24 -0700223#define DTV_ENUM_DELSYS 44
224#define DTV_ATSCMH_FIC_VER 45
225#define DTV_ATSCMH_PARADE_ID 46
226#define DTV_ATSCMH_NOG 47
Ben Cheng655a7c02013-10-16 16:09:24 -0700227#define DTV_ATSCMH_TNOG 48
228#define DTV_ATSCMH_SGN 49
229#define DTV_ATSCMH_PRC 50
230#define DTV_ATSCMH_RS_FRAME_MODE 51
Ben Cheng655a7c02013-10-16 16:09:24 -0700231#define DTV_ATSCMH_RS_FRAME_ENSEMBLE 52
232#define DTV_ATSCMH_RS_CODE_MODE_PRI 53
233#define DTV_ATSCMH_RS_CODE_MODE_SEC 54
234#define DTV_ATSCMH_SCCC_BLOCK_MODE 55
Ben Cheng655a7c02013-10-16 16:09:24 -0700235#define DTV_ATSCMH_SCCC_CODE_MODE_A 56
236#define DTV_ATSCMH_SCCC_CODE_MODE_B 57
237#define DTV_ATSCMH_SCCC_CODE_MODE_C 58
238#define DTV_ATSCMH_SCCC_CODE_MODE_D 59
Ben Cheng655a7c02013-10-16 16:09:24 -0700239#define DTV_INTERLEAVING 60
240#define DTV_LNA 61
241#define DTV_STAT_SIGNAL_STRENGTH 62
242#define DTV_STAT_CNR 63
Ben Cheng655a7c02013-10-16 16:09:24 -0700243#define DTV_STAT_PRE_ERROR_BIT_COUNT 64
244#define DTV_STAT_PRE_TOTAL_BIT_COUNT 65
245#define DTV_STAT_POST_ERROR_BIT_COUNT 66
246#define DTV_STAT_POST_TOTAL_BIT_COUNT 67
Ben Cheng655a7c02013-10-16 16:09:24 -0700247#define DTV_STAT_ERROR_BLOCK_COUNT 68
248#define DTV_STAT_TOTAL_BLOCK_COUNT 69
249#define DTV_MAX_COMMAND DTV_STAT_TOTAL_BLOCK_COUNT
Christopher Ferris05d08e92016-02-04 13:16:38 -0800250enum fe_pilot {
Tao Baod7db5942015-01-28 10:07:51 -0800251 PILOT_ON,
252 PILOT_OFF,
253 PILOT_AUTO,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800254};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800255enum fe_rolloff {
Tao Baod7db5942015-01-28 10:07:51 -0800256 ROLLOFF_35,
257 ROLLOFF_20,
258 ROLLOFF_25,
Tao Baod7db5942015-01-28 10:07:51 -0800259 ROLLOFF_AUTO,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800260};
261enum fe_delivery_system {
Tao Baod7db5942015-01-28 10:07:51 -0800262 SYS_UNDEFINED,
Tao Baod7db5942015-01-28 10:07:51 -0800263 SYS_DVBC_ANNEX_A,
264 SYS_DVBC_ANNEX_B,
265 SYS_DVBT,
266 SYS_DSS,
Tao Baod7db5942015-01-28 10:07:51 -0800267 SYS_DVBS,
268 SYS_DVBS2,
269 SYS_DVBH,
270 SYS_ISDBT,
Tao Baod7db5942015-01-28 10:07:51 -0800271 SYS_ISDBS,
272 SYS_ISDBC,
273 SYS_ATSC,
274 SYS_ATSCMH,
Tao Baod7db5942015-01-28 10:07:51 -0800275 SYS_DTMB,
276 SYS_CMMB,
277 SYS_DAB,
278 SYS_DVBT2,
Tao Baod7db5942015-01-28 10:07:51 -0800279 SYS_TURBO,
280 SYS_DVBC_ANNEX_C,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800281};
Ben Cheng655a7c02013-10-16 16:09:24 -0700282#define SYS_DVBC_ANNEX_AC SYS_DVBC_ANNEX_A
Ben Cheng655a7c02013-10-16 16:09:24 -0700283#define SYS_DMBTH SYS_DTMB
284enum atscmh_sccc_block_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800285 ATSCMH_SCCC_BLK_SEP = 0,
286 ATSCMH_SCCC_BLK_COMB = 1,
Tao Baod7db5942015-01-28 10:07:51 -0800287 ATSCMH_SCCC_BLK_RES = 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700288};
289enum atscmh_sccc_code_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800290 ATSCMH_SCCC_CODE_HLF = 0,
Tao Baod7db5942015-01-28 10:07:51 -0800291 ATSCMH_SCCC_CODE_QTR = 1,
292 ATSCMH_SCCC_CODE_RES = 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700293};
294enum atscmh_rs_frame_ensemble {
Tao Baod7db5942015-01-28 10:07:51 -0800295 ATSCMH_RSFRAME_ENS_PRI = 0,
296 ATSCMH_RSFRAME_ENS_SEC = 1,
Ben Cheng655a7c02013-10-16 16:09:24 -0700297};
298enum atscmh_rs_frame_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800299 ATSCMH_RSFRAME_PRI_ONLY = 0,
300 ATSCMH_RSFRAME_PRI_SEC = 1,
301 ATSCMH_RSFRAME_RES = 2,
Ben Cheng655a7c02013-10-16 16:09:24 -0700302};
Ben Cheng655a7c02013-10-16 16:09:24 -0700303enum atscmh_rs_code_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800304 ATSCMH_RSCODE_211_187 = 0,
305 ATSCMH_RSCODE_223_187 = 1,
306 ATSCMH_RSCODE_235_187 = 2,
Tao Baod7db5942015-01-28 10:07:51 -0800307 ATSCMH_RSCODE_RES = 3,
Ben Cheng655a7c02013-10-16 16:09:24 -0700308};
309#define NO_STREAM_ID_FILTER (~0U)
310#define LNA_AUTO (~0U)
Ben Cheng655a7c02013-10-16 16:09:24 -0700311struct dtv_cmds_h {
Tao Baod7db5942015-01-28 10:07:51 -0800312 char * name;
313 __u32 cmd;
314 __u32 set : 1;
Tao Baod7db5942015-01-28 10:07:51 -0800315 __u32 buffer : 1;
316 __u32 reserved : 30;
Ben Cheng655a7c02013-10-16 16:09:24 -0700317};
318enum fecap_scale_params {
Tao Baod7db5942015-01-28 10:07:51 -0800319 FE_SCALE_NOT_AVAILABLE = 0,
320 FE_SCALE_DECIBEL,
321 FE_SCALE_RELATIVE,
322 FE_SCALE_COUNTER
Ben Cheng655a7c02013-10-16 16:09:24 -0700323};
324struct dtv_stats {
Tao Baod7db5942015-01-28 10:07:51 -0800325 __u8 scale;
326 union {
Tao Baod7db5942015-01-28 10:07:51 -0800327 __u64 uvalue;
328 __s64 svalue;
329 };
330} __attribute__((packed));
Ben Cheng655a7c02013-10-16 16:09:24 -0700331#define MAX_DTV_STATS 4
332struct dtv_fe_stats {
Tao Baod7db5942015-01-28 10:07:51 -0800333 __u8 len;
334 struct dtv_stats stat[MAX_DTV_STATS];
Tao Baod7db5942015-01-28 10:07:51 -0800335} __attribute__((packed));
Ben Cheng655a7c02013-10-16 16:09:24 -0700336struct dtv_property {
Tao Baod7db5942015-01-28 10:07:51 -0800337 __u32 cmd;
338 __u32 reserved[3];
Tao Baod7db5942015-01-28 10:07:51 -0800339 union {
340 __u32 data;
341 struct dtv_fe_stats st;
342 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800343 __u8 data[32];
344 __u32 len;
345 __u32 reserved1[3];
346 void * reserved2;
Tao Baod7db5942015-01-28 10:07:51 -0800347 } buffer;
348 } u;
349 int result;
350} __attribute__((packed));
Ben Cheng655a7c02013-10-16 16:09:24 -0700351#define DTV_IOCTL_MAX_MSGS 64
352struct dtv_properties {
Tao Baod7db5942015-01-28 10:07:51 -0800353 __u32 num;
354 struct dtv_property * props;
Ben Cheng655a7c02013-10-16 16:09:24 -0700355};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800356enum fe_bandwidth {
357 BANDWIDTH_8_MHZ,
358 BANDWIDTH_7_MHZ,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800359 BANDWIDTH_6_MHZ,
360 BANDWIDTH_AUTO,
361 BANDWIDTH_5_MHZ,
362 BANDWIDTH_10_MHZ,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800363 BANDWIDTH_1_712_MHZ,
364};
365typedef enum fe_sec_voltage fe_sec_voltage_t;
366typedef enum fe_caps fe_caps_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800367typedef enum fe_type fe_type_t;
368typedef enum fe_sec_tone_mode fe_sec_tone_mode_t;
369typedef enum fe_sec_mini_cmd fe_sec_mini_cmd_t;
370typedef enum fe_status fe_status_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800371typedef enum fe_spectral_inversion fe_spectral_inversion_t;
372typedef enum fe_code_rate fe_code_rate_t;
373typedef enum fe_modulation fe_modulation_t;
374typedef enum fe_transmit_mode fe_transmit_mode_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800375typedef enum fe_bandwidth fe_bandwidth_t;
376typedef enum fe_guard_interval fe_guard_interval_t;
377typedef enum fe_hierarchy fe_hierarchy_t;
378typedef enum fe_pilot fe_pilot_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800379typedef enum fe_rolloff fe_rolloff_t;
380typedef enum fe_delivery_system fe_delivery_system_t;
381struct dvb_qpsk_parameters {
382 __u32 symbol_rate;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800383 fe_code_rate_t fec_inner;
384};
385struct dvb_qam_parameters {
386 __u32 symbol_rate;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800387 fe_code_rate_t fec_inner;
388 fe_modulation_t modulation;
389};
390struct dvb_vsb_parameters {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800391 fe_modulation_t modulation;
392};
393struct dvb_ofdm_parameters {
394 fe_bandwidth_t bandwidth;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800395 fe_code_rate_t code_rate_HP;
396 fe_code_rate_t code_rate_LP;
397 fe_modulation_t constellation;
398 fe_transmit_mode_t transmission_mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800399 fe_guard_interval_t guard_interval;
400 fe_hierarchy_t hierarchy_information;
401};
402struct dvb_frontend_parameters {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800403 __u32 frequency;
404 fe_spectral_inversion_t inversion;
405 union {
406 struct dvb_qpsk_parameters qpsk;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800407 struct dvb_qam_parameters qam;
408 struct dvb_ofdm_parameters ofdm;
409 struct dvb_vsb_parameters vsb;
410 } u;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800411};
412struct dvb_frontend_event {
413 fe_status_t status;
414 struct dvb_frontend_parameters parameters;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800415};
Ben Cheng655a7c02013-10-16 16:09:24 -0700416#define FE_SET_PROPERTY _IOW('o', 82, struct dtv_properties)
417#define FE_GET_PROPERTY _IOR('o', 83, struct dtv_properties)
418#define FE_TUNE_MODE_ONESHOT 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700419#define FE_GET_INFO _IOR('o', 61, struct dvb_frontend_info)
420#define FE_DISEQC_RESET_OVERLOAD _IO('o', 62)
421#define FE_DISEQC_SEND_MASTER_CMD _IOW('o', 63, struct dvb_diseqc_master_cmd)
422#define FE_DISEQC_RECV_SLAVE_REPLY _IOR('o', 64, struct dvb_diseqc_slave_reply)
Ben Cheng655a7c02013-10-16 16:09:24 -0700423#define FE_DISEQC_SEND_BURST _IO('o', 65)
424#define FE_SET_TONE _IO('o', 66)
425#define FE_SET_VOLTAGE _IO('o', 67)
426#define FE_ENABLE_HIGH_LNB_VOLTAGE _IO('o', 68)
Ben Cheng655a7c02013-10-16 16:09:24 -0700427#define FE_READ_STATUS _IOR('o', 69, fe_status_t)
428#define FE_READ_BER _IOR('o', 70, __u32)
429#define FE_READ_SIGNAL_STRENGTH _IOR('o', 71, __u16)
430#define FE_READ_SNR _IOR('o', 72, __u16)
Ben Cheng655a7c02013-10-16 16:09:24 -0700431#define FE_READ_UNCORRECTED_BLOCKS _IOR('o', 73, __u32)
432#define FE_SET_FRONTEND _IOW('o', 76, struct dvb_frontend_parameters)
433#define FE_GET_FRONTEND _IOR('o', 77, struct dvb_frontend_parameters)
434#define FE_SET_FRONTEND_TUNE_MODE _IO('o', 81)
Ben Cheng655a7c02013-10-16 16:09:24 -0700435#define FE_GET_EVENT _IOR('o', 78, struct dvb_frontend_event)
436#define FE_DISHNETWORK_SEND_LEGACY_CMD _IO('o', 80)
437#endif