blob: de30d629fb16298b3bb1f59a0c63d76f49501a82 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __R128_DRM_H__
20#define __R128_DRM_H__
Christopher Ferris05d08e92016-02-04 13:16:38 -080021#include <drm/drm.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070022#ifndef __R128_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -070023/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080024#define __R128_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -070025#define R128_UPLOAD_CONTEXT 0x001
26#define R128_UPLOAD_SETUP 0x002
27#define R128_UPLOAD_TEX0 0x004
Ben Cheng655a7c02013-10-16 16:09:24 -070028/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080029#define R128_UPLOAD_TEX1 0x008
Ben Cheng655a7c02013-10-16 16:09:24 -070030#define R128_UPLOAD_TEX0IMAGES 0x010
31#define R128_UPLOAD_TEX1IMAGES 0x020
32#define R128_UPLOAD_CORE 0x040
Ben Cheng655a7c02013-10-16 16:09:24 -070033/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080034#define R128_UPLOAD_MASKS 0x080
Ben Cheng655a7c02013-10-16 16:09:24 -070035#define R128_UPLOAD_WINDOW 0x100
36#define R128_UPLOAD_CLIPRECTS 0x200
37#define R128_REQUIRE_QUIESCENCE 0x400
Ben Cheng655a7c02013-10-16 16:09:24 -070038/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080039#define R128_UPLOAD_ALL 0x7ff
Ben Cheng655a7c02013-10-16 16:09:24 -070040#define R128_FRONT 0x1
41#define R128_BACK 0x2
42#define R128_DEPTH 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -070043/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080044#define R128_POINTS 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -070045#define R128_LINES 0x2
46#define R128_LINE_STRIP 0x3
47#define R128_TRIANGLES 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -070048/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080049#define R128_TRIANGLE_FAN 0x5
Ben Cheng655a7c02013-10-16 16:09:24 -070050#define R128_TRIANGLE_STRIP 0x6
51#define R128_BUFFER_SIZE 16384
52#define R128_INDEX_PRIM_OFFSET 20
Ben Cheng655a7c02013-10-16 16:09:24 -070053/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080054#define R128_HOSTDATA_BLIT_OFFSET 32
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define R128_NR_SAREA_CLIPRECTS 12
56#define R128_LOCAL_TEX_HEAP 0
57#define R128_AGP_TEX_HEAP 1
Ben Cheng655a7c02013-10-16 16:09:24 -070058/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080059#define R128_NR_TEX_HEAPS 2
Ben Cheng655a7c02013-10-16 16:09:24 -070060#define R128_NR_TEX_REGIONS 64
61#define R128_LOG_TEX_GRANULARITY 16
62#define R128_NR_CONTEXT_REGS 12
Ben Cheng655a7c02013-10-16 16:09:24 -070063/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080064#define R128_MAX_TEXTURE_LEVELS 11
Ben Cheng655a7c02013-10-16 16:09:24 -070065#define R128_MAX_TEXTURE_UNITS 2
66#endif
67typedef struct {
Ben Cheng655a7c02013-10-16 16:09:24 -070068/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080069 unsigned int dst_pitch_offset_c;
Tao Baod7db5942015-01-28 10:07:51 -080070 unsigned int dp_gui_master_cntl_c;
71 unsigned int sc_top_left_c;
72 unsigned int sc_bottom_right_c;
Ben Cheng655a7c02013-10-16 16:09:24 -070073/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080074 unsigned int z_offset_c;
Tao Baod7db5942015-01-28 10:07:51 -080075 unsigned int z_pitch_c;
76 unsigned int z_sten_cntl_c;
77 unsigned int tex_cntl_c;
Ben Cheng655a7c02013-10-16 16:09:24 -070078/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080079 unsigned int misc_3d_state_cntl_reg;
Tao Baod7db5942015-01-28 10:07:51 -080080 unsigned int texture_clr_cmp_clr_c;
81 unsigned int texture_clr_cmp_msk_c;
82 unsigned int fog_color_c;
Ben Cheng655a7c02013-10-16 16:09:24 -070083/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080084 unsigned int tex_size_pitch_c;
Tao Baod7db5942015-01-28 10:07:51 -080085 unsigned int constant_color_c;
86 unsigned int pm4_vc_fpu_setup;
87 unsigned int setup_cntl;
Ben Cheng655a7c02013-10-16 16:09:24 -070088/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080089 unsigned int dp_write_mask;
Tao Baod7db5942015-01-28 10:07:51 -080090 unsigned int sten_ref_mask_c;
91 unsigned int plane_3d_mask_c;
92 unsigned int window_xy_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -070093/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080094 unsigned int scale_3d_cntl;
Ben Cheng655a7c02013-10-16 16:09:24 -070095} drm_r128_context_regs_t;
96typedef struct {
Tao Baod7db5942015-01-28 10:07:51 -080097 unsigned int tex_cntl;
Ben Cheng655a7c02013-10-16 16:09:24 -070098/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -080099 unsigned int tex_combine_cntl;
Tao Baod7db5942015-01-28 10:07:51 -0800100 unsigned int tex_size_pitch;
101 unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
102 unsigned int tex_border_color;
Ben Cheng655a7c02013-10-16 16:09:24 -0700103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800104} drm_r128_texture_regs_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700105typedef struct drm_r128_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800106 drm_r128_context_regs_t context_state;
107 drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800109 unsigned int dirty;
Tao Baod7db5942015-01-28 10:07:51 -0800110 unsigned int vertsize;
111 unsigned int vc_format;
112 struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
Ben Cheng655a7c02013-10-16 16:09:24 -0700113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800114 unsigned int nbox;
Tao Baod7db5942015-01-28 10:07:51 -0800115 unsigned int last_frame;
116 unsigned int last_dispatch;
117 struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
Ben Cheng655a7c02013-10-16 16:09:24 -0700118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800119 unsigned int tex_age[R128_NR_TEX_HEAPS];
Tao Baod7db5942015-01-28 10:07:51 -0800120 int ctx_owner;
121 int pfAllowPageFlip;
122 int pfCurrentPage;
Ben Cheng655a7c02013-10-16 16:09:24 -0700123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800124} drm_r128_sarea_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700125#define DRM_R128_INIT 0x00
126#define DRM_R128_CCE_START 0x01
127#define DRM_R128_CCE_STOP 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800129#define DRM_R128_CCE_RESET 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700130#define DRM_R128_CCE_IDLE 0x04
131#define DRM_R128_RESET 0x06
132#define DRM_R128_SWAP 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800134#define DRM_R128_CLEAR 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700135#define DRM_R128_VERTEX 0x09
136#define DRM_R128_INDICES 0x0a
137#define DRM_R128_BLIT 0x0b
Ben Cheng655a7c02013-10-16 16:09:24 -0700138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800139#define DRM_R128_DEPTH 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700140#define DRM_R128_STIPPLE 0x0d
141#define DRM_R128_INDIRECT 0x0f
142#define DRM_R128_FULLSCREEN 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800144#define DRM_R128_CLEAR2 0x11
Ben Cheng655a7c02013-10-16 16:09:24 -0700145#define DRM_R128_GETPARAM 0x12
146#define DRM_R128_FLIP 0x13
Tao Baod7db5942015-01-28 10:07:51 -0800147#define DRM_IOCTL_R128_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800149#define DRM_IOCTL_R128_CCE_START DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_START)
Tao Baod7db5942015-01-28 10:07:51 -0800150#define DRM_IOCTL_R128_CCE_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
151#define DRM_IOCTL_R128_CCE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
152#define DRM_IOCTL_R128_CCE_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
Ben Cheng655a7c02013-10-16 16:09:24 -0700153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800154#define DRM_IOCTL_R128_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_RESET)
Tao Baod7db5942015-01-28 10:07:51 -0800155#define DRM_IOCTL_R128_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_R128_SWAP)
156#define DRM_IOCTL_R128_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
157#define DRM_IOCTL_R128_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800159#define DRM_IOCTL_R128_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
Tao Baod7db5942015-01-28 10:07:51 -0800160#define DRM_IOCTL_R128_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
161#define DRM_IOCTL_R128_DEPTH DRM_IOW(DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
162#define DRM_IOCTL_R128_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800164#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
Tao Baod7db5942015-01-28 10:07:51 -0800165#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
166#define DRM_IOCTL_R128_CLEAR2 DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
167#define DRM_IOCTL_R128_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800169#define DRM_IOCTL_R128_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_R128_FLIP)
Ben Cheng655a7c02013-10-16 16:09:24 -0700170typedef struct drm_r128_init {
Tao Baod7db5942015-01-28 10:07:51 -0800171 enum {
172 R128_INIT_CCE = 0x01,
Ben Cheng655a7c02013-10-16 16:09:24 -0700173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800174 R128_CLEANUP_CCE = 0x02
Tao Baod7db5942015-01-28 10:07:51 -0800175 } func;
176 unsigned long sarea_priv_offset;
177 int is_pci;
Ben Cheng655a7c02013-10-16 16:09:24 -0700178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800179 int cce_mode;
Tao Baod7db5942015-01-28 10:07:51 -0800180 int cce_secure;
181 int ring_size;
182 int usec_timeout;
Ben Cheng655a7c02013-10-16 16:09:24 -0700183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800184 unsigned int fb_bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800185 unsigned int front_offset, front_pitch;
186 unsigned int back_offset, back_pitch;
187 unsigned int depth_bpp;
Ben Cheng655a7c02013-10-16 16:09:24 -0700188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800189 unsigned int depth_offset, depth_pitch;
Tao Baod7db5942015-01-28 10:07:51 -0800190 unsigned int span_offset;
191 unsigned long fb_offset;
192 unsigned long mmio_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800194 unsigned long ring_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800195 unsigned long ring_rptr_offset;
196 unsigned long buffers_offset;
197 unsigned long agp_textures_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800199} drm_r128_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700200typedef struct drm_r128_cce_stop {
Tao Baod7db5942015-01-28 10:07:51 -0800201 int flush;
202 int idle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800204} drm_r128_cce_stop_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700205typedef struct drm_r128_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800206 unsigned int flags;
207 unsigned int clear_color;
Ben Cheng655a7c02013-10-16 16:09:24 -0700208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800209 unsigned int clear_depth;
Tao Baod7db5942015-01-28 10:07:51 -0800210 unsigned int color_mask;
211 unsigned int depth_mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700212} drm_r128_clear_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800214typedef struct drm_r128_vertex {
Tao Baod7db5942015-01-28 10:07:51 -0800215 int prim;
216 int idx;
217 int count;
Ben Cheng655a7c02013-10-16 16:09:24 -0700218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800219 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700220} drm_r128_vertex_t;
221typedef struct drm_r128_indices {
Tao Baod7db5942015-01-28 10:07:51 -0800222 int prim;
Ben Cheng655a7c02013-10-16 16:09:24 -0700223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800224 int idx;
Tao Baod7db5942015-01-28 10:07:51 -0800225 int start;
226 int end;
227 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800229} drm_r128_indices_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700230typedef struct drm_r128_blit {
Tao Baod7db5942015-01-28 10:07:51 -0800231 int idx;
232 int pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -0700233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800234 int offset;
Tao Baod7db5942015-01-28 10:07:51 -0800235 int format;
236 unsigned short x, y;
237 unsigned short width, height;
Ben Cheng655a7c02013-10-16 16:09:24 -0700238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800239} drm_r128_blit_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700240typedef struct drm_r128_depth {
Tao Baod7db5942015-01-28 10:07:51 -0800241 enum {
242 R128_WRITE_SPAN = 0x01,
Ben Cheng655a7c02013-10-16 16:09:24 -0700243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800244 R128_WRITE_PIXELS = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800245 R128_READ_SPAN = 0x03,
246 R128_READ_PIXELS = 0x04
247 } func;
Ben Cheng655a7c02013-10-16 16:09:24 -0700248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800249 int n;
Tao Baod7db5942015-01-28 10:07:51 -0800250 int __user * x;
251 int __user * y;
252 unsigned int __user * buffer;
Ben Cheng655a7c02013-10-16 16:09:24 -0700253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800254 unsigned char __user * mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700255} drm_r128_depth_t;
256typedef struct drm_r128_stipple {
Tao Baod7db5942015-01-28 10:07:51 -0800257 unsigned int __user * mask;
Ben Cheng655a7c02013-10-16 16:09:24 -0700258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800259} drm_r128_stipple_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700260typedef struct drm_r128_indirect {
Tao Baod7db5942015-01-28 10:07:51 -0800261 int idx;
262 int start;
Ben Cheng655a7c02013-10-16 16:09:24 -0700263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800264 int end;
Tao Baod7db5942015-01-28 10:07:51 -0800265 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700266} drm_r128_indirect_t;
267typedef struct drm_r128_fullscreen {
Ben Cheng655a7c02013-10-16 16:09:24 -0700268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800269 enum {
Tao Baod7db5942015-01-28 10:07:51 -0800270 R128_INIT_FULLSCREEN = 0x01,
271 R128_CLEANUP_FULLSCREEN = 0x02
272 } func;
Ben Cheng655a7c02013-10-16 16:09:24 -0700273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800274} drm_r128_fullscreen_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700275#define R128_PARAM_IRQ_NR 1
276typedef struct drm_r128_getparam {
Tao Baod7db5942015-01-28 10:07:51 -0800277 int param;
Ben Cheng655a7c02013-10-16 16:09:24 -0700278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800279 void __user * value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700280} drm_r128_getparam_t;
281#endif