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gerrit.omnirom.org / android_bionic / 6a25dff8a3af1b4720bc7ac77c37bb9833b5a616 / . / libc / kernel / uapi / drm / qaic_accel.h
blob: 3e6bb2ae2ab4658e8523ae2de04f16e15188e62e [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +0000[diff] [blame]1/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Christopher Ferris37c3f3c2023-07-10 10:59:05 -0700[diff] [blame]7#ifndef QAIC_ACCEL_H_
8#define QAIC_ACCEL_H_
9#include "drm.h"
10#ifdef __cplusplus
11extern "C" {
12#endif
13#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K
14#define QAIC_SEM_INSYNCFENCE 2
15#define QAIC_SEM_OUTSYNCFENCE 1
16#define QAIC_SEM_NOP 0
17#define QAIC_SEM_INIT 1
18#define QAIC_SEM_INC 2
19#define QAIC_SEM_DEC 3
20#define QAIC_SEM_WAIT_EQUAL 4
21#define QAIC_SEM_WAIT_GT_EQ 5
22#define QAIC_SEM_WAIT_GT_0 6
23#define QAIC_TRANS_UNDEFINED 0
24#define QAIC_TRANS_PASSTHROUGH_FROM_USR 1
25#define QAIC_TRANS_PASSTHROUGH_TO_USR 2
26#define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3
27#define QAIC_TRANS_PASSTHROUGH_TO_DEV 4
28#define QAIC_TRANS_DMA_XFER_FROM_USR 5
29#define QAIC_TRANS_DMA_XFER_TO_DEV 6
30#define QAIC_TRANS_ACTIVATE_FROM_USR 7
31#define QAIC_TRANS_ACTIVATE_FROM_DEV 8
32#define QAIC_TRANS_ACTIVATE_TO_DEV 9
33#define QAIC_TRANS_DEACTIVATE_FROM_USR 10
34#define QAIC_TRANS_DEACTIVATE_FROM_DEV 11
35#define QAIC_TRANS_STATUS_FROM_USR 12
36#define QAIC_TRANS_STATUS_TO_USR 13
37#define QAIC_TRANS_STATUS_FROM_DEV 14
38#define QAIC_TRANS_STATUS_TO_DEV 15
39#define QAIC_TRANS_TERMINATE_FROM_DEV 16
40#define QAIC_TRANS_TERMINATE_TO_DEV 17
41#define QAIC_TRANS_DMA_XFER_CONT 18
42#define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19
43#define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20
44struct qaic_manage_trans_hdr {
45 __u32 type;
46 __u32 len;
47};
48struct qaic_manage_trans_passthrough {
49 struct qaic_manage_trans_hdr hdr;
50 __u8 data[];
51};
52struct qaic_manage_trans_dma_xfer {
53 struct qaic_manage_trans_hdr hdr;
54 __u32 tag;
55 __u32 pad;
56 __u64 addr;
57 __u64 size;
58};
59struct qaic_manage_trans_activate_to_dev {
60 struct qaic_manage_trans_hdr hdr;
61 __u32 queue_size;
62 __u32 eventfd;
63 __u32 options;
64 __u32 pad;
65};
66struct qaic_manage_trans_activate_from_dev {
67 struct qaic_manage_trans_hdr hdr;
68 __u32 status;
69 __u32 dbc_id;
70 __u64 options;
71};
72struct qaic_manage_trans_deactivate {
73 struct qaic_manage_trans_hdr hdr;
74 __u32 dbc_id;
75 __u32 pad;
76};
77struct qaic_manage_trans_status_to_dev {
78 struct qaic_manage_trans_hdr hdr;
79};
80struct qaic_manage_trans_status_from_dev {
81 struct qaic_manage_trans_hdr hdr;
82 __u16 major;
83 __u16 minor;
84 __u32 status;
85 __u64 status_flags;
86};
87struct qaic_manage_msg {
88 __u32 len;
89 __u32 count;
90 __u64 data;
91};
92struct qaic_create_bo {
93 __u64 size;
94 __u32 handle;
95 __u32 pad;
96};
97struct qaic_mmap_bo {
98 __u32 handle;
99 __u32 pad;
100 __u64 offset;
101};
102struct qaic_sem {
103 __u16 val;
104 __u8 index;
105 __u8 presync;
106 __u8 cmd;
107 __u8 flags;
108 __u16 pad;
109};
110struct qaic_attach_slice_entry {
111 __u64 size;
112 struct qaic_sem sem0;
113 struct qaic_sem sem1;
114 struct qaic_sem sem2;
115 struct qaic_sem sem3;
116 __u64 dev_addr;
117 __u64 db_addr;
118 __u32 db_data;
119 __u32 db_len;
120 __u64 offset;
121};
122struct qaic_attach_slice_hdr {
123 __u32 count;
124 __u32 dbc_id;
125 __u32 handle;
126 __u32 dir;
127 __u64 size;
128};
129struct qaic_attach_slice {
130 struct qaic_attach_slice_hdr hdr;
131 __u64 data;
132};
133struct qaic_execute_entry {
134 __u32 handle;
135 __u32 dir;
136};
137struct qaic_partial_execute_entry {
138 __u32 handle;
139 __u32 dir;
140 __u64 resize;
141};
142struct qaic_execute_hdr {
143 __u32 count;
144 __u32 dbc_id;
145};
146struct qaic_execute {
147 struct qaic_execute_hdr hdr;
148 __u64 data;
149};
150struct qaic_wait {
151 __u32 handle;
152 __u32 timeout;
153 __u32 dbc_id;
154 __u32 pad;
155};
156struct qaic_perf_stats_hdr {
157 __u16 count;
158 __u16 pad;
159 __u32 dbc_id;
160};
161struct qaic_perf_stats {
162 struct qaic_perf_stats_hdr hdr;
163 __u64 data;
164};
165struct qaic_perf_stats_entry {
166 __u32 handle;
167 __u32 queue_level_before;
168 __u32 num_queue_element;
169 __u32 submit_latency_us;
170 __u32 device_latency_us;
171 __u32 pad;
172};
173#define DRM_QAIC_MANAGE 0x00
174#define DRM_QAIC_CREATE_BO 0x01
175#define DRM_QAIC_MMAP_BO 0x02
176#define DRM_QAIC_ATTACH_SLICE_BO 0x03
177#define DRM_QAIC_EXECUTE_BO 0x04
178#define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05
179#define DRM_QAIC_WAIT_BO 0x06
180#define DRM_QAIC_PERF_STATS_BO 0x07
181#define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg)
182#define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo)
183#define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo)
184#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice)
185#define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute)
186#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute)
187#define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait)
188#define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats)
189#ifdef __cplusplus
190}
191#endif
192#endif