AArch64: Add initial support for AArch64
This is the first patch out of a series of patches that add support for
AArch64, the new 64bit execution state of the ARMv8 Architecture. The
patches add support for LP64 programming model.
The patch adds:
* "arch-aarch64" to the architecture directories.
* "arch-aarch64/include" - headers used by libc
* "arch-aarch64/bionic":
- crtbegin, crtend support;
- aarch64 specific syscall stubs;
- setjmp, clone, vfork assembly files.
Change-Id: If72b859f81928d03ad05d4ccfcb54c2f5dbf99a5
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
diff --git a/libc/private/__get_tls.h b/libc/private/__get_tls.h
index 5f9451d..04c5fdb 100644
--- a/libc/private/__get_tls.h
+++ b/libc/private/__get_tls.h
@@ -29,11 +29,10 @@
#ifndef __BIONIC_PRIVATE_GET_TLS_H_
#define __BIONIC_PRIVATE_GET_TLS_H_
-#if defined(__arm__)
-# define __get_tls() \
- ({ void** __val; \
- __asm__("mrc p15, 0, %0, c13, c0, 3" : "=r"(__val)); \
- __val; })
+#if defined(__aarch64__)
+# define __get_tls() ({ void** __val; __asm__("mrs %0, tpidr_el0" : "=r"(__val)); __val; })
+#elif defined(__arm__)
+# define __get_tls() ({ void** __val; __asm__("mrc p15, 0, %0, c13, c0, 3" : "=r"(__val)); __val; })
#elif defined(__mips__)
# define __get_tls() \
/* On mips32r1, this goes via a kernel illegal instruction trap that's optimized for v1. */ \
@@ -44,15 +43,9 @@
".set pop\n" : "=r"(__val)); \
__val; })
#elif defined(__i386__)
-# define __get_tls() \
- ({ void** __val; \
- __asm__("movl %%gs:0, %0" : "=r"(__val)); \
- __val; })
+# define __get_tls() ({ void** __val; __asm__("movl %%gs:0, %0" : "=r"(__val)); __val; })
#elif defined(__x86_64__)
-# define __get_tls() \
- ({ void** __val; \
- __asm__("mov %%fs:0, %0" : "=r"(__val)); \
- __val; })
+# define __get_tls() ({ void** __val; __asm__("mov %%fs:0, %0" : "=r"(__val)); __val; })
#else
#error unsupported architecture
#endif