diff --git a/libc/kernel/uapi/drm/armada_drm.h b/libc/kernel/uapi/drm/armada_drm.h
index efd7dd4..160c4f8 100644
--- a/libc/kernel/uapi/drm/armada_drm.h
+++ b/libc/kernel/uapi/drm/armada_drm.h
@@ -22,30 +22,30 @@
 #define DRM_ARMADA_GEM_MMAP 0x02
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_ARMADA_GEM_PWRITE 0x03
-#define ARMADA_IOCTL(dir, name, str)   DRM_##dir(DRM_COMMAND_BASE + DRM_ARMADA_##name, struct drm_armada_##str)
+#define ARMADA_IOCTL(dir,name,str) DRM_ ##dir(DRM_COMMAND_BASE + DRM_ARMADA_ ##name, struct drm_armada_ ##str)
 struct drm_armada_gem_create {
- uint32_t handle;
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t size;
+  uint32_t size;
 };
-#define DRM_IOCTL_ARMADA_GEM_CREATE   ARMADA_IOCTL(IOWR, GEM_CREATE, gem_create)
+#define DRM_IOCTL_ARMADA_GEM_CREATE ARMADA_IOCTL(IOWR, GEM_CREATE, gem_create)
 struct drm_armada_gem_mmap {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t pad;
- uint64_t offset;
- uint64_t size;
+  uint32_t handle;
+  uint32_t pad;
+  uint64_t offset;
+  uint64_t size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t addr;
+  uint64_t addr;
 };
-#define DRM_IOCTL_ARMADA_GEM_MMAP   ARMADA_IOCTL(IOWR, GEM_MMAP, gem_mmap)
+#define DRM_IOCTL_ARMADA_GEM_MMAP ARMADA_IOCTL(IOWR, GEM_MMAP, gem_mmap)
 struct drm_armada_gem_pwrite {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t ptr;
- uint32_t handle;
- uint32_t offset;
- uint32_t size;
+  uint64_t ptr;
+  uint32_t handle;
+  uint32_t offset;
+  uint32_t size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
-#define DRM_IOCTL_ARMADA_GEM_PWRITE   ARMADA_IOCTL(IOW, GEM_PWRITE, gem_pwrite)
+#define DRM_IOCTL_ARMADA_GEM_PWRITE ARMADA_IOCTL(IOW, GEM_PWRITE, gem_pwrite)
 #endif
diff --git a/libc/kernel/uapi/drm/drm.h b/libc/kernel/uapi/drm/drm.h
index 32a76a7..8efc7d7 100644
--- a/libc/kernel/uapi/drm/drm.h
+++ b/libc/kernel/uapi/drm/drm.h
@@ -49,376 +49,376 @@
 #define _DRM_LOCK_CONT 0x40000000U
 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
-#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
+#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD | _DRM_LOCK_CONT))
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef unsigned int drm_context_t;
 typedef unsigned int drm_drawable_t;
 typedef unsigned int drm_magic_t;
 struct drm_clip_rect {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned short x1;
- unsigned short y1;
- unsigned short x2;
- unsigned short y2;
+  unsigned short x1;
+  unsigned short y1;
+  unsigned short x2;
+  unsigned short y2;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_drawable_info {
- unsigned int num_rects;
- struct drm_clip_rect *rects;
+  unsigned int num_rects;
+  struct drm_clip_rect * rects;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_tex_region {
- unsigned char next;
- unsigned char prev;
+  unsigned char next;
+  unsigned char prev;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned char in_use;
- unsigned char padding;
- unsigned int age;
+  unsigned char in_use;
+  unsigned char padding;
+  unsigned int age;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_hw_lock {
- __volatile__ unsigned int lock;
- char padding[60];
+  __volatile__ unsigned int lock;
+  char padding[60];
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_version {
- int version_major;
- int version_minor;
- int version_patchlevel;
+  int version_major;
+  int version_minor;
+  int version_patchlevel;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- size_t name_len;
- char __user *name;
- size_t date_len;
- char __user *date;
+  size_t name_len;
+  char __user * name;
+  size_t date_len;
+  char __user * date;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- size_t desc_len;
- char __user *desc;
+  size_t desc_len;
+  char __user * desc;
 };
 struct drm_unique {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- size_t unique_len;
- char __user *unique;
+  size_t unique_len;
+  char __user * unique;
 };
 struct drm_list {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int count;
- struct drm_version __user *version;
+  int count;
+  struct drm_version __user * version;
 };
 struct drm_block {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int unused;
+  int unused;
 };
 struct drm_control {
- enum {
+  enum {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- DRM_ADD_COMMAND,
- DRM_RM_COMMAND,
- DRM_INST_HANDLER,
- DRM_UNINST_HANDLER
+    DRM_ADD_COMMAND,
+    DRM_RM_COMMAND,
+    DRM_INST_HANDLER,
+    DRM_UNINST_HANDLER
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } func;
- int irq;
+  } func;
+  int irq;
 };
 enum drm_map_type {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_FRAME_BUFFER = 0,
- _DRM_REGISTERS = 1,
- _DRM_SHM = 2,
- _DRM_AGP = 3,
+  _DRM_FRAME_BUFFER = 0,
+  _DRM_REGISTERS = 1,
+  _DRM_SHM = 2,
+  _DRM_AGP = 3,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_SCATTER_GATHER = 4,
- _DRM_CONSISTENT = 5,
+  _DRM_SCATTER_GATHER = 4,
+  _DRM_CONSISTENT = 5,
 };
 enum drm_map_flags {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_RESTRICTED = 0x01,
- _DRM_READ_ONLY = 0x02,
- _DRM_LOCKED = 0x04,
- _DRM_KERNEL = 0x08,
+  _DRM_RESTRICTED = 0x01,
+  _DRM_READ_ONLY = 0x02,
+  _DRM_LOCKED = 0x04,
+  _DRM_KERNEL = 0x08,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_WRITE_COMBINING = 0x10,
- _DRM_CONTAINS_LOCK = 0x20,
- _DRM_REMOVABLE = 0x40,
- _DRM_DRIVER = 0x80
+  _DRM_WRITE_COMBINING = 0x10,
+  _DRM_CONTAINS_LOCK = 0x20,
+  _DRM_REMOVABLE = 0x40,
+  _DRM_DRIVER = 0x80
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_ctx_priv_map {
- unsigned int ctx_id;
- void *handle;
+  unsigned int ctx_id;
+  void * handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_map {
- unsigned long offset;
- unsigned long size;
+  unsigned long offset;
+  unsigned long size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- enum drm_map_type type;
- enum drm_map_flags flags;
- void *handle;
- int mtrr;
+  enum drm_map_type type;
+  enum drm_map_flags flags;
+  void * handle;
+  int mtrr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_client {
- int idx;
- int auth;
+  int idx;
+  int auth;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long pid;
- unsigned long uid;
- unsigned long magic;
- unsigned long iocs;
+  unsigned long pid;
+  unsigned long uid;
+  unsigned long magic;
+  unsigned long iocs;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 enum drm_stat_type {
- _DRM_STAT_LOCK,
- _DRM_STAT_OPENS,
+  _DRM_STAT_LOCK,
+  _DRM_STAT_OPENS,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_STAT_CLOSES,
- _DRM_STAT_IOCTLS,
- _DRM_STAT_LOCKS,
- _DRM_STAT_UNLOCKS,
+  _DRM_STAT_CLOSES,
+  _DRM_STAT_IOCTLS,
+  _DRM_STAT_LOCKS,
+  _DRM_STAT_UNLOCKS,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_STAT_VALUE,
- _DRM_STAT_BYTE,
- _DRM_STAT_COUNT,
- _DRM_STAT_IRQ,
+  _DRM_STAT_VALUE,
+  _DRM_STAT_BYTE,
+  _DRM_STAT_COUNT,
+  _DRM_STAT_IRQ,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_STAT_PRIMARY,
- _DRM_STAT_SECONDARY,
- _DRM_STAT_DMA,
- _DRM_STAT_SPECIAL,
+  _DRM_STAT_PRIMARY,
+  _DRM_STAT_SECONDARY,
+  _DRM_STAT_DMA,
+  _DRM_STAT_SPECIAL,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_STAT_MISSED
+  _DRM_STAT_MISSED
 };
 struct drm_stats {
- unsigned long count;
+  unsigned long count;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct {
- unsigned long value;
- enum drm_stat_type type;
- } data[15];
+  struct {
+    unsigned long value;
+    enum drm_stat_type type;
+  } data[15];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 enum drm_lock_flags {
- _DRM_LOCK_READY = 0x01,
- _DRM_LOCK_QUIESCENT = 0x02,
+  _DRM_LOCK_READY = 0x01,
+  _DRM_LOCK_QUIESCENT = 0x02,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_LOCK_FLUSH = 0x04,
- _DRM_LOCK_FLUSH_ALL = 0x08,
- _DRM_HALT_ALL_QUEUES = 0x10,
- _DRM_HALT_CUR_QUEUES = 0x20
+  _DRM_LOCK_FLUSH = 0x04,
+  _DRM_LOCK_FLUSH_ALL = 0x08,
+  _DRM_HALT_ALL_QUEUES = 0x10,
+  _DRM_HALT_CUR_QUEUES = 0x20
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_lock {
- int context;
- enum drm_lock_flags flags;
+  int context;
+  enum drm_lock_flags flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 enum drm_dma_flags {
- _DRM_DMA_BLOCK = 0x01,
- _DRM_DMA_WHILE_LOCKED = 0x02,
+  _DRM_DMA_BLOCK = 0x01,
+  _DRM_DMA_WHILE_LOCKED = 0x02,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_DMA_PRIORITY = 0x04,
- _DRM_DMA_WAIT = 0x10,
- _DRM_DMA_SMALLER_OK = 0x20,
- _DRM_DMA_LARGER_OK = 0x40
+  _DRM_DMA_PRIORITY = 0x04,
+  _DRM_DMA_WAIT = 0x10,
+  _DRM_DMA_SMALLER_OK = 0x20,
+  _DRM_DMA_LARGER_OK = 0x40
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_buf_desc {
- int count;
- int size;
+  int count;
+  int size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int low_mark;
- int high_mark;
- enum {
- _DRM_PAGE_ALIGN = 0x01,
+  int low_mark;
+  int high_mark;
+  enum {
+    _DRM_PAGE_ALIGN = 0x01,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_AGP_BUFFER = 0x02,
- _DRM_SG_BUFFER = 0x04,
- _DRM_FB_BUFFER = 0x08,
- _DRM_PCI_BUFFER_RO = 0x10
+    _DRM_AGP_BUFFER = 0x02,
+    _DRM_SG_BUFFER = 0x04,
+    _DRM_FB_BUFFER = 0x08,
+    _DRM_PCI_BUFFER_RO = 0x10
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } flags;
- unsigned long agp_start;
+  } flags;
+  unsigned long agp_start;
 };
 struct drm_buf_info {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int count;
- struct drm_buf_desc __user *list;
+  int count;
+  struct drm_buf_desc __user * list;
 };
 struct drm_buf_free {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int count;
- int __user *list;
+  int count;
+  int __user * list;
 };
 struct drm_buf_pub {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int idx;
- int total;
- int used;
- void __user *address;
+  int idx;
+  int total;
+  int used;
+  void __user * address;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_buf_map {
- int count;
- void __user *virtual;
+  int count;
+  void __user * virtual;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_buf_pub __user *list;
+  struct drm_buf_pub __user * list;
 };
 struct drm_dma {
- int context;
+  int context;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int send_count;
- int __user *send_indices;
- int __user *send_sizes;
- enum drm_dma_flags flags;
+  int send_count;
+  int __user * send_indices;
+  int __user * send_sizes;
+  enum drm_dma_flags flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int request_count;
- int request_size;
- int __user *request_indices;
- int __user *request_sizes;
+  int request_count;
+  int request_size;
+  int __user * request_indices;
+  int __user * request_sizes;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int granted_count;
+  int granted_count;
 };
 enum drm_ctx_flags {
- _DRM_CONTEXT_PRESERVED = 0x01,
+  _DRM_CONTEXT_PRESERVED = 0x01,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_CONTEXT_2DONLY = 0x02
+  _DRM_CONTEXT_2DONLY = 0x02
 };
 struct drm_ctx {
- drm_context_t handle;
+  drm_context_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- enum drm_ctx_flags flags;
+  enum drm_ctx_flags flags;
 };
 struct drm_ctx_res {
- int count;
+  int count;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_ctx __user *contexts;
+  struct drm_ctx __user * contexts;
 };
 struct drm_draw {
- drm_drawable_t handle;
+  drm_drawable_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 typedef enum {
- DRM_DRAWABLE_CLIPRECTS,
+  DRM_DRAWABLE_CLIPRECTS,
 } drm_drawable_info_type_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_update_draw {
- drm_drawable_t handle;
- unsigned int type;
- unsigned int num;
+  drm_drawable_t handle;
+  unsigned int type;
+  unsigned int num;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long long data;
+  unsigned long long data;
 };
 struct drm_auth {
- drm_magic_t magic;
+  drm_magic_t magic;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_irq_busid {
- int irq;
- int busnum;
+  int irq;
+  int busnum;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int devnum;
- int funcnum;
+  int devnum;
+  int funcnum;
 };
 enum drm_vblank_seq_type {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_VBLANK_ABSOLUTE = 0x0,
- _DRM_VBLANK_RELATIVE = 0x1,
- _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
- _DRM_VBLANK_EVENT = 0x4000000,
+  _DRM_VBLANK_ABSOLUTE = 0x0,
+  _DRM_VBLANK_RELATIVE = 0x1,
+  _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
+  _DRM_VBLANK_EVENT = 0x4000000,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- _DRM_VBLANK_FLIP = 0x8000000,
- _DRM_VBLANK_NEXTONMISS = 0x10000000,
- _DRM_VBLANK_SECONDARY = 0x20000000,
- _DRM_VBLANK_SIGNAL = 0x40000000
+  _DRM_VBLANK_FLIP = 0x8000000,
+  _DRM_VBLANK_NEXTONMISS = 0x10000000,
+  _DRM_VBLANK_SECONDARY = 0x20000000,
+  _DRM_VBLANK_SIGNAL = 0x40000000
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
-#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL |   _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
+#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_wait_vblank_request {
- enum drm_vblank_seq_type type;
- unsigned int sequence;
- unsigned long signal;
+  enum drm_vblank_seq_type type;
+  unsigned int sequence;
+  unsigned long signal;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_wait_vblank_reply {
- enum drm_vblank_seq_type type;
- unsigned int sequence;
+  enum drm_vblank_seq_type type;
+  unsigned int sequence;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- long tval_sec;
- long tval_usec;
+  long tval_sec;
+  long tval_usec;
 };
 union drm_wait_vblank {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_wait_vblank_request request;
- struct drm_wait_vblank_reply reply;
+  struct drm_wait_vblank_request request;
+  struct drm_wait_vblank_reply reply;
 };
 #define _DRM_PRE_MODESET 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define _DRM_POST_MODESET 2
 struct drm_modeset_ctl {
- __u32 crtc;
- __u32 cmd;
+  __u32 crtc;
+  __u32 cmd;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_agp_mode {
- unsigned long mode;
+  unsigned long mode;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_agp_buffer {
- unsigned long size;
- unsigned long handle;
- unsigned long type;
+  unsigned long size;
+  unsigned long handle;
+  unsigned long type;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long physical;
+  unsigned long physical;
 };
 struct drm_agp_binding {
- unsigned long handle;
+  unsigned long handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long offset;
+  unsigned long offset;
 };
 struct drm_agp_info {
- int agp_version_major;
+  int agp_version_major;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int agp_version_minor;
- unsigned long mode;
- unsigned long aperture_base;
- unsigned long aperture_size;
+  int agp_version_minor;
+  unsigned long mode;
+  unsigned long aperture_base;
+  unsigned long aperture_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long memory_allowed;
- unsigned long memory_used;
- unsigned short id_vendor;
- unsigned short id_device;
+  unsigned long memory_allowed;
+  unsigned long memory_used;
+  unsigned short id_vendor;
+  unsigned short id_device;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_scatter_gather {
- unsigned long size;
- unsigned long handle;
+  unsigned long size;
+  unsigned long handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_set_version {
- int drm_di_major;
- int drm_di_minor;
+  int drm_di_major;
+  int drm_di_minor;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int drm_dd_major;
- int drm_dd_minor;
+  int drm_dd_major;
+  int drm_dd_minor;
 };
 struct drm_gem_close {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
- __u32 pad;
+  __u32 handle;
+  __u32 pad;
 };
 struct drm_gem_flink {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
- __u32 name;
+  __u32 handle;
+  __u32 name;
 };
 struct drm_gem_open {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 name;
- __u32 handle;
- __u64 size;
+  __u32 name;
+  __u32 handle;
+  __u64 size;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_CAP_DUMB_BUFFER 0x1
@@ -436,65 +436,65 @@
 #define DRM_CAP_CURSOR_HEIGHT 0x9
 struct drm_get_cap {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 capability;
- __u64 value;
+  __u64 capability;
+  __u64 value;
 };
 #define DRM_CLIENT_CAP_STEREO_3D 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
 struct drm_set_client_cap {
- __u64 capability;
- __u64 value;
+  __u64 capability;
+  __u64 value;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define DRM_CLOEXEC O_CLOEXEC
 struct drm_prime_handle {
- __u32 handle;
+  __u32 handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 flags;
- __s32 fd;
+  __u32 flags;
+  __s32 fd;
 };
 #include <drm/drm_mode.h>
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_BASE 'd'
-#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
-#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
-#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
+#define DRM_IO(nr) _IO(DRM_IOCTL_BASE, nr)
+#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE, nr, type)
+#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE, nr, type)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
+#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE, nr, type)
 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
-#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
+#define DRM_IOCTL_GET_MAGIC DRM_IOR(0x02, struct drm_auth)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
-#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
+#define DRM_IOCTL_GET_STATS DRM_IOR(0x06, struct drm_stats)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
-#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
+#define DRM_IOCTL_GEM_CLOSE DRM_IOW(0x09, struct drm_gem_close)
 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
 #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
-#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)
-#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
+#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW(0x0d, struct drm_set_client_cap)
+#define DRM_IOCTL_SET_UNIQUE DRM_IOW(0x10, struct drm_unique)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
+#define DRM_IOCTL_AUTH_MAGIC DRM_IOW(0x11, struct drm_auth)
 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
-#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
+#define DRM_IOCTL_CONTROL DRM_IOW(0x14, struct drm_control)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
-#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
+#define DRM_IOCTL_MARK_BUFS DRM_IOW(0x17, struct drm_buf_desc)
 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
-#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
-#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
-#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
+#define DRM_IOCTL_FREE_BUFS DRM_IOW(0x1a, struct drm_buf_free)
+#define DRM_IOCTL_RM_MAP DRM_IOW(0x1b, struct drm_map)
+#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW(0x1c, struct drm_ctx_priv_map)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
 #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
@@ -502,34 +502,34 @@
 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
-#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
+#define DRM_IOCTL_MOD_CTX DRM_IOW(0x22, struct drm_ctx)
 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
-#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
+#define DRM_IOCTL_SWITCH_CTX DRM_IOW(0x24, struct drm_ctx)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
+#define DRM_IOCTL_NEW_CTX DRM_IOW(0x25, struct drm_ctx)
 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
-#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
-#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
-#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
+#define DRM_IOCTL_LOCK DRM_IOW(0x2a, struct drm_lock)
+#define DRM_IOCTL_UNLOCK DRM_IOW(0x2b, struct drm_lock)
+#define DRM_IOCTL_FINISH DRM_IOW(0x2c, struct drm_lock)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
 #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
-#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
-#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
+#define DRM_IOCTL_AGP_ACQUIRE DRM_IO(0x30)
+#define DRM_IOCTL_AGP_RELEASE DRM_IO(0x31)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
-#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
+#define DRM_IOCTL_AGP_ENABLE DRM_IOW(0x32, struct drm_agp_mode)
+#define DRM_IOCTL_AGP_INFO DRM_IOR(0x33, struct drm_agp_info)
 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
-#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
+#define DRM_IOCTL_AGP_FREE DRM_IOW(0x35, struct drm_agp_buffer)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
-#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
+#define DRM_IOCTL_AGP_BIND DRM_IOW(0x36, struct drm_agp_binding)
+#define DRM_IOCTL_AGP_UNBIND DRM_IOW(0x37, struct drm_agp_binding)
 #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
-#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
+#define DRM_IOCTL_SG_FREE DRM_IOW(0x39, struct drm_scatter_gather)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
@@ -572,21 +572,21 @@
 #define DRM_COMMAND_END 0xA0
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_event {
- __u32 type;
- __u32 length;
+  __u32 type;
+  __u32 length;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_EVENT_VBLANK 0x01
 #define DRM_EVENT_FLIP_COMPLETE 0x02
 struct drm_event_vblank {
- struct drm_event base;
+  struct drm_event base;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 user_data;
- __u32 tv_sec;
- __u32 tv_usec;
- __u32 sequence;
+  __u64 user_data;
+  __u32 tv_sec;
+  __u32 tv_usec;
+  __u32 sequence;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 reserved;
+  __u32 reserved;
 };
 typedef struct drm_clip_rect drm_clip_rect_t;
 typedef struct drm_drawable_info drm_drawable_info_t;
diff --git a/libc/kernel/uapi/drm/drm_fourcc.h b/libc/kernel/uapi/drm/drm_fourcc.h
index e4acf17..47e93dd 100644
--- a/libc/kernel/uapi/drm/drm_fourcc.h
+++ b/libc/kernel/uapi/drm/drm_fourcc.h
@@ -19,9 +19,9 @@
 #ifndef DRM_FOURCC_H
 #define DRM_FOURCC_H
 #include <linux/types.h>
-#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) |   ((__u32)(c) << 16) | ((__u32)(d) << 24))
+#define fourcc_code(a,b,c,d) ((__u32) (a) | ((__u32) (b) << 8) | ((__u32) (c) << 16) | ((__u32) (d) << 24))
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_FORMAT_BIG_ENDIAN (1<<31)
+#define DRM_FORMAT_BIG_ENDIAN (1 << 31)
 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ')
 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8')
 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8')
diff --git a/libc/kernel/uapi/drm/drm_mode.h b/libc/kernel/uapi/drm/drm_mode.h
index 4a69518..abd92a1 100644
--- a/libc/kernel/uapi/drm/drm_mode.h
+++ b/libc/kernel/uapi/drm/drm_mode.h
@@ -24,45 +24,45 @@
 #define DRM_CONNECTOR_NAME_LEN 32
 #define DRM_DISPLAY_MODE_LEN 32
 #define DRM_PROP_NAME_LEN 32
-#define DRM_MODE_TYPE_BUILTIN (1<<0)
+#define DRM_MODE_TYPE_BUILTIN (1 << 0)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
-#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
-#define DRM_MODE_TYPE_PREFERRED (1<<3)
-#define DRM_MODE_TYPE_DEFAULT (1<<4)
+#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
+#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
+#define DRM_MODE_TYPE_PREFERRED (1 << 3)
+#define DRM_MODE_TYPE_DEFAULT (1 << 4)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_TYPE_USERDEF (1<<5)
-#define DRM_MODE_TYPE_DRIVER (1<<6)
-#define DRM_MODE_FLAG_PHSYNC (1<<0)
-#define DRM_MODE_FLAG_NHSYNC (1<<1)
+#define DRM_MODE_TYPE_USERDEF (1 << 5)
+#define DRM_MODE_TYPE_DRIVER (1 << 6)
+#define DRM_MODE_FLAG_PHSYNC (1 << 0)
+#define DRM_MODE_FLAG_NHSYNC (1 << 1)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_FLAG_PVSYNC (1<<2)
-#define DRM_MODE_FLAG_NVSYNC (1<<3)
-#define DRM_MODE_FLAG_INTERLACE (1<<4)
-#define DRM_MODE_FLAG_DBLSCAN (1<<5)
+#define DRM_MODE_FLAG_PVSYNC (1 << 2)
+#define DRM_MODE_FLAG_NVSYNC (1 << 3)
+#define DRM_MODE_FLAG_INTERLACE (1 << 4)
+#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_FLAG_CSYNC (1<<6)
-#define DRM_MODE_FLAG_PCSYNC (1<<7)
-#define DRM_MODE_FLAG_NCSYNC (1<<8)
-#define DRM_MODE_FLAG_HSKEW (1<<9)
+#define DRM_MODE_FLAG_CSYNC (1 << 6)
+#define DRM_MODE_FLAG_PCSYNC (1 << 7)
+#define DRM_MODE_FLAG_NCSYNC (1 << 8)
+#define DRM_MODE_FLAG_HSKEW (1 << 9)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_FLAG_BCAST (1<<10)
-#define DRM_MODE_FLAG_PIXMUX (1<<11)
-#define DRM_MODE_FLAG_DBLCLK (1<<12)
-#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
+#define DRM_MODE_FLAG_BCAST (1 << 10)
+#define DRM_MODE_FLAG_PIXMUX (1 << 11)
+#define DRM_MODE_FLAG_DBLCLK (1 << 12)
+#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
-#define DRM_MODE_FLAG_3D_NONE (0<<14)
-#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
-#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)
+#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
+#define DRM_MODE_FLAG_3D_NONE (0 << 14)
+#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
+#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)
-#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)
-#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)
-#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
+#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
+#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
+#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
+#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
-#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
+#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
+#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
 #define DRM_MODE_DPMS_ON 0
 #define DRM_MODE_DPMS_STANDBY 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -86,73 +86,73 @@
 #define DRM_MODE_DIRTY_ANNOTATE 2
 struct drm_mode_modeinfo {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 clock;
- __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
- __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
- __u32 vrefresh;
+  __u32 clock;
+  __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
+  __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
+  __u32 vrefresh;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 flags;
- __u32 type;
- char name[DRM_DISPLAY_MODE_LEN];
+  __u32 flags;
+  __u32 type;
+  char name[DRM_DISPLAY_MODE_LEN];
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_mode_card_res {
- __u64 fb_id_ptr;
- __u64 crtc_id_ptr;
- __u64 connector_id_ptr;
+  __u64 fb_id_ptr;
+  __u64 crtc_id_ptr;
+  __u64 connector_id_ptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 encoder_id_ptr;
- __u32 count_fbs;
- __u32 count_crtcs;
- __u32 count_connectors;
+  __u64 encoder_id_ptr;
+  __u32 count_fbs;
+  __u32 count_crtcs;
+  __u32 count_connectors;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 count_encoders;
- __u32 min_width, max_width;
- __u32 min_height, max_height;
+  __u32 count_encoders;
+  __u32 min_width, max_width;
+  __u32 min_height, max_height;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_mode_crtc {
- __u64 set_connectors_ptr;
- __u32 count_connectors;
- __u32 crtc_id;
+  __u64 set_connectors_ptr;
+  __u32 count_connectors;
+  __u32 crtc_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 fb_id;
- __u32 x, y;
- __u32 gamma_size;
- __u32 mode_valid;
+  __u32 fb_id;
+  __u32 x, y;
+  __u32 gamma_size;
+  __u32 mode_valid;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_mode_modeinfo mode;
+  struct drm_mode_modeinfo mode;
 };
-#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
-#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
+#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
+#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_mode_set_plane {
- __u32 plane_id;
- __u32 crtc_id;
- __u32 fb_id;
+  __u32 plane_id;
+  __u32 crtc_id;
+  __u32 fb_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 flags;
- __s32 crtc_x, crtc_y;
- __u32 crtc_w, crtc_h;
- __u32 src_x, src_y;
+  __u32 flags;
+  __s32 crtc_x, crtc_y;
+  __u32 crtc_w, crtc_h;
+  __u32 src_x, src_y;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 src_h, src_w;
+  __u32 src_h, src_w;
 };
 struct drm_mode_get_plane {
- __u32 plane_id;
+  __u32 plane_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 crtc_id;
- __u32 fb_id;
- __u32 possible_crtcs;
- __u32 gamma_size;
+  __u32 crtc_id;
+  __u32 fb_id;
+  __u32 possible_crtcs;
+  __u32 gamma_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 count_format_types;
- __u64 format_type_ptr;
+  __u32 count_format_types;
+  __u64 format_type_ptr;
 };
 struct drm_mode_get_plane_res {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 plane_id_ptr;
- __u32 count_planes;
+  __u64 plane_id_ptr;
+  __u32 count_planes;
 };
 #define DRM_MODE_ENCODER_NONE 0
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -166,12 +166,12 @@
 #define DRM_MODE_ENCODER_DPMST 7
 struct drm_mode_get_encoder {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 encoder_id;
- __u32 encoder_type;
- __u32 crtc_id;
- __u32 possible_crtcs;
+  __u32 encoder_id;
+  __u32 encoder_type;
+  __u32 crtc_id;
+  __u32 possible_crtcs;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 possible_clones;
+  __u32 possible_clones;
 };
 #define DRM_MODE_SUBCONNECTOR_Automatic 0
 #define DRM_MODE_SUBCONNECTOR_Unknown 0
@@ -206,34 +206,34 @@
 #define DRM_MODE_CONNECTOR_DSI 16
 struct drm_mode_get_connector {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 encoders_ptr;
- __u64 modes_ptr;
- __u64 props_ptr;
- __u64 prop_values_ptr;
+  __u64 encoders_ptr;
+  __u64 modes_ptr;
+  __u64 props_ptr;
+  __u64 prop_values_ptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 count_modes;
- __u32 count_props;
- __u32 count_encoders;
- __u32 encoder_id;
+  __u32 count_modes;
+  __u32 count_props;
+  __u32 count_encoders;
+  __u32 encoder_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 connector_id;
- __u32 connector_type;
- __u32 connector_type_id;
- __u32 connection;
+  __u32 connector_id;
+  __u32 connector_type;
+  __u32 connector_type_id;
+  __u32 connection;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 mm_width, mm_height;
- __u32 subpixel;
- __u32 pad;
+  __u32 mm_width, mm_height;
+  __u32 subpixel;
+  __u32 pad;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_PROP_PENDING (1<<0)
-#define DRM_MODE_PROP_RANGE (1<<1)
-#define DRM_MODE_PROP_IMMUTABLE (1<<2)
-#define DRM_MODE_PROP_ENUM (1<<3)
+#define DRM_MODE_PROP_PENDING (1 << 0)
+#define DRM_MODE_PROP_RANGE (1 << 1)
+#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
+#define DRM_MODE_PROP_ENUM (1 << 3)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_PROP_BLOB (1<<4)
-#define DRM_MODE_PROP_BITMASK (1<<5)
-#define DRM_MODE_PROP_LEGACY_TYPE (   DRM_MODE_PROP_RANGE |   DRM_MODE_PROP_ENUM |   DRM_MODE_PROP_BLOB |   DRM_MODE_PROP_BITMASK)
+#define DRM_MODE_PROP_BLOB (1 << 4)
+#define DRM_MODE_PROP_BITMASK (1 << 5)
+#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
 #define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_MODE_PROP_TYPE(n) ((n) << 6)
@@ -241,70 +241,70 @@
 #define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
 struct drm_mode_property_enum {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 value;
- char name[DRM_PROP_NAME_LEN];
+  __u64 value;
+  char name[DRM_PROP_NAME_LEN];
 };
 struct drm_mode_get_property {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 values_ptr;
- __u64 enum_blob_ptr;
- __u32 prop_id;
- __u32 flags;
+  __u64 values_ptr;
+  __u64 enum_blob_ptr;
+  __u32 prop_id;
+  __u32 flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- char name[DRM_PROP_NAME_LEN];
- __u32 count_values;
- __u32 count_enum_blobs;
+  char name[DRM_PROP_NAME_LEN];
+  __u32 count_values;
+  __u32 count_enum_blobs;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_mode_connector_set_property {
- __u64 value;
- __u32 prop_id;
- __u32 connector_id;
+  __u64 value;
+  __u32 prop_id;
+  __u32 connector_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_mode_obj_get_properties {
- __u64 props_ptr;
- __u64 prop_values_ptr;
+  __u64 props_ptr;
+  __u64 prop_values_ptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 count_props;
- __u32 obj_id;
- __u32 obj_type;
+  __u32 count_props;
+  __u32 obj_id;
+  __u32 obj_type;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_mode_obj_set_property {
- __u64 value;
- __u32 prop_id;
- __u32 obj_id;
+  __u64 value;
+  __u32 prop_id;
+  __u32 obj_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 obj_type;
+  __u32 obj_type;
 };
 struct drm_mode_get_blob {
- __u32 blob_id;
+  __u32 blob_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 length;
- __u64 data;
+  __u32 length;
+  __u64 data;
 };
 struct drm_mode_fb_cmd {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 fb_id;
- __u32 width, height;
- __u32 pitch;
- __u32 bpp;
+  __u32 fb_id;
+  __u32 width, height;
+  __u32 pitch;
+  __u32 bpp;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 depth;
- __u32 handle;
+  __u32 depth;
+  __u32 handle;
 };
-#define DRM_MODE_FB_INTERLACED (1<<0)
+#define DRM_MODE_FB_INTERLACED (1 << 0)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_mode_fb_cmd2 {
- __u32 fb_id;
- __u32 width, height;
- __u32 pixel_format;
+  __u32 fb_id;
+  __u32 width, height;
+  __u32 pixel_format;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 flags;
- __u32 handles[4];
- __u32 pitches[4];
- __u32 offsets[4];
+  __u32 flags;
+  __u32 handles[4];
+  __u32 pitches[4];
+  __u32 offsets[4];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
@@ -313,17 +313,17 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
 struct drm_mode_fb_dirty_cmd {
- __u32 fb_id;
- __u32 flags;
+  __u32 fb_id;
+  __u32 flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 color;
- __u32 num_clips;
- __u64 clips_ptr;
+  __u32 color;
+  __u32 num_clips;
+  __u64 clips_ptr;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_mode_mode_cmd {
- __u32 connector_id;
- struct drm_mode_modeinfo mode;
+  __u32 connector_id;
+  struct drm_mode_modeinfo mode;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_MODE_CURSOR_BO 0x01
@@ -331,70 +331,70 @@
 #define DRM_MODE_CURSOR_FLAGS 0x03
 struct drm_mode_cursor {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 flags;
- __u32 crtc_id;
- __s32 x;
- __s32 y;
+  __u32 flags;
+  __u32 crtc_id;
+  __s32 x;
+  __s32 y;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 width;
- __u32 height;
- __u32 handle;
+  __u32 width;
+  __u32 height;
+  __u32 handle;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_mode_cursor2 {
- __u32 flags;
- __u32 crtc_id;
- __s32 x;
+  __u32 flags;
+  __u32 crtc_id;
+  __s32 x;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __s32 y;
- __u32 width;
- __u32 height;
- __u32 handle;
+  __s32 y;
+  __u32 width;
+  __u32 height;
+  __u32 handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __s32 hot_x;
- __s32 hot_y;
+  __s32 hot_x;
+  __s32 hot_y;
 };
 struct drm_mode_crtc_lut {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 crtc_id;
- __u32 gamma_size;
- __u64 red;
- __u64 green;
+  __u32 crtc_id;
+  __u32 gamma_size;
+  __u64 red;
+  __u64 green;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 blue;
+  __u64 blue;
 };
 #define DRM_MODE_PAGE_FLIP_EVENT 0x01
 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)
+#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC)
 struct drm_mode_crtc_page_flip {
- __u32 crtc_id;
- __u32 fb_id;
+  __u32 crtc_id;
+  __u32 fb_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 flags;
- __u32 reserved;
- __u64 user_data;
+  __u32 flags;
+  __u32 reserved;
+  __u64 user_data;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_mode_create_dumb {
- uint32_t height;
- uint32_t width;
- uint32_t bpp;
+  uint32_t height;
+  uint32_t width;
+  uint32_t bpp;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t flags;
- uint32_t handle;
- uint32_t pitch;
- uint64_t size;
+  uint32_t flags;
+  uint32_t handle;
+  uint32_t pitch;
+  uint64_t size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_mode_map_dumb {
- __u32 handle;
- __u32 pad;
+  __u32 handle;
+  __u32 pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 offset;
+  __u64 offset;
 };
 struct drm_mode_destroy_dumb {
- uint32_t handle;
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #endif
diff --git a/libc/kernel/uapi/drm/drm_sarea.h b/libc/kernel/uapi/drm/drm_sarea.h
index ecf4440..ca19c2b 100644
--- a/libc/kernel/uapi/drm/drm_sarea.h
+++ b/libc/kernel/uapi/drm/drm_sarea.h
@@ -34,26 +34,26 @@
 #define SAREA_MAX_DRAWABLES 256
 #define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
 struct drm_sarea_drawable {
- unsigned int stamp;
+  unsigned int stamp;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int flags;
+  unsigned int flags;
 };
 struct drm_sarea_frame {
- unsigned int x;
+  unsigned int x;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int y;
- unsigned int width;
- unsigned int height;
- unsigned int fullscreen;
+  unsigned int y;
+  unsigned int width;
+  unsigned int height;
+  unsigned int fullscreen;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_sarea {
- struct drm_hw_lock lock;
- struct drm_hw_lock drawable_lock;
+  struct drm_hw_lock lock;
+  struct drm_hw_lock drawable_lock;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES];
- struct drm_sarea_frame frame;
- drm_context_t dummy_context;
+  struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES];
+  struct drm_sarea_frame frame;
+  drm_context_t dummy_context;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_sarea_drawable drm_sarea_drawable_t;
diff --git a/libc/kernel/uapi/drm/exynos_drm.h b/libc/kernel/uapi/drm/exynos_drm.h
index 85e7f04..47294b7 100644
--- a/libc/kernel/uapi/drm/exynos_drm.h
+++ b/libc/kernel/uapi/drm/exynos_drm.h
@@ -21,243 +21,240 @@
 #include <drm/drm.h>
 struct drm_exynos_gem_create {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t size;
- unsigned int flags;
- unsigned int handle;
+  uint64_t size;
+  unsigned int flags;
+  unsigned int handle;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_exynos_gem_info {
- unsigned int handle;
- unsigned int flags;
- uint64_t size;
+  unsigned int handle;
+  unsigned int flags;
+  uint64_t size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_exynos_vidi_connection {
- unsigned int connection;
- unsigned int extensions;
+  unsigned int connection;
+  unsigned int extensions;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t edid;
+  uint64_t edid;
 };
 enum e_drm_exynos_gem_mem_type {
- EXYNOS_BO_CONTIG = 0 << 0,
+  EXYNOS_BO_CONTIG = 0 << 0,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- EXYNOS_BO_NONCONTIG = 1 << 0,
- EXYNOS_BO_NONCACHABLE = 0 << 1,
- EXYNOS_BO_CACHABLE = 1 << 1,
- EXYNOS_BO_WC = 1 << 2,
+  EXYNOS_BO_NONCONTIG = 1 << 0,
+  EXYNOS_BO_NONCACHABLE = 0 << 1,
+  EXYNOS_BO_CACHABLE = 1 << 1,
+  EXYNOS_BO_WC = 1 << 2,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
- EXYNOS_BO_WC
+  EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | EXYNOS_BO_WC
 };
 struct drm_exynos_g2d_get_ver {
+  __u32 major;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 major;
- __u32 minor;
+  __u32 minor;
 };
 struct drm_exynos_g2d_cmd {
+  __u32 offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 offset;
- __u32 data;
+  __u32 data;
 };
 enum drm_exynos_g2d_buf_type {
+  G2D_BUF_USERPTR = 1 << 31,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- G2D_BUF_USERPTR = 1 << 31,
 };
 enum drm_exynos_g2d_event_type {
- G2D_EVENT_NOT,
+  G2D_EVENT_NOT,
+  G2D_EVENT_NONSTOP,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- G2D_EVENT_NONSTOP,
- G2D_EVENT_STOP,
+  G2D_EVENT_STOP,
 };
 struct drm_exynos_g2d_userptr {
+  unsigned long userptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long userptr;
- unsigned long size;
+  unsigned long size;
 };
 struct drm_exynos_g2d_set_cmdlist {
+  __u64 cmd;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 cmd;
- __u64 cmd_buf;
- __u32 cmd_nr;
- __u32 cmd_buf_nr;
+  __u64 cmd_buf;
+  __u32 cmd_nr;
+  __u32 cmd_buf_nr;
+  __u64 event_type;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 event_type;
- __u64 user_data;
+  __u64 user_data;
 };
 struct drm_exynos_g2d_exec {
+  __u64 async;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 async;
 };
 enum drm_exynos_ops_id {
- EXYNOS_DRM_OPS_SRC,
+  EXYNOS_DRM_OPS_SRC,
+  EXYNOS_DRM_OPS_DST,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- EXYNOS_DRM_OPS_DST,
- EXYNOS_DRM_OPS_MAX,
+  EXYNOS_DRM_OPS_MAX,
 };
 struct drm_exynos_sz {
+  __u32 hsize;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 hsize;
- __u32 vsize;
+  __u32 vsize;
 };
 struct drm_exynos_pos {
+  __u32 x;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 x;
- __u32 y;
- __u32 w;
- __u32 h;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  __u32 y;
+  __u32 w;
+  __u32 h;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum drm_exynos_flip {
- EXYNOS_DRM_FLIP_NONE = (0 << 0),
- EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
+  EXYNOS_DRM_FLIP_NONE = (0 << 0),
+  EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
+  EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
- EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
- EXYNOS_DRM_FLIP_HORIZONTAL,
+  EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | EXYNOS_DRM_FLIP_HORIZONTAL,
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum drm_exynos_degree {
- EXYNOS_DRM_DEGREE_0,
- EXYNOS_DRM_DEGREE_90,
- EXYNOS_DRM_DEGREE_180,
+  EXYNOS_DRM_DEGREE_0,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- EXYNOS_DRM_DEGREE_270,
+  EXYNOS_DRM_DEGREE_90,
+  EXYNOS_DRM_DEGREE_180,
+  EXYNOS_DRM_DEGREE_270,
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum drm_exynos_planer {
- EXYNOS_DRM_PLANAR_Y,
+  EXYNOS_DRM_PLANAR_Y,
+  EXYNOS_DRM_PLANAR_CB,
+  EXYNOS_DRM_PLANAR_CR,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- EXYNOS_DRM_PLANAR_CB,
- EXYNOS_DRM_PLANAR_CR,
- EXYNOS_DRM_PLANAR_MAX,
+  EXYNOS_DRM_PLANAR_MAX,
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_exynos_ipp_prop_list {
- __u32 version;
- __u32 ipp_id;
- __u32 count;
+  __u32 version;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 writeback;
- __u32 flip;
- __u32 degree;
- __u32 csc;
+  __u32 ipp_id;
+  __u32 count;
+  __u32 writeback;
+  __u32 flip;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 crop;
- __u32 scale;
- __u32 refresh_min;
- __u32 refresh_max;
+  __u32 degree;
+  __u32 csc;
+  __u32 crop;
+  __u32 scale;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 reserved;
- struct drm_exynos_sz crop_min;
- struct drm_exynos_sz crop_max;
- struct drm_exynos_sz scale_min;
+  __u32 refresh_min;
+  __u32 refresh_max;
+  __u32 reserved;
+  struct drm_exynos_sz crop_min;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_exynos_sz scale_max;
+  struct drm_exynos_sz crop_max;
+  struct drm_exynos_sz scale_min;
+  struct drm_exynos_sz scale_max;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_exynos_ipp_config {
- enum drm_exynos_ops_id ops_id;
+  enum drm_exynos_ops_id ops_id;
+  enum drm_exynos_flip flip;
+  enum drm_exynos_degree degree;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- enum drm_exynos_flip flip;
- enum drm_exynos_degree degree;
- __u32 fmt;
- struct drm_exynos_sz sz;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_exynos_pos pos;
+  __u32 fmt;
+  struct drm_exynos_sz sz;
+  struct drm_exynos_pos pos;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum drm_exynos_ipp_cmd {
- IPP_CMD_NONE,
+  IPP_CMD_NONE,
+  IPP_CMD_M2M,
+  IPP_CMD_WB,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- IPP_CMD_M2M,
- IPP_CMD_WB,
- IPP_CMD_OUTPUT,
- IPP_CMD_MAX,
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  IPP_CMD_OUTPUT,
+  IPP_CMD_MAX,
 };
 struct drm_exynos_ipp_property {
- struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
- enum drm_exynos_ipp_cmd cmd;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 ipp_id;
- __u32 prop_id;
- __u32 refresh_rate;
+  struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
+  enum drm_exynos_ipp_cmd cmd;
+  __u32 ipp_id;
+  __u32 prop_id;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  __u32 refresh_rate;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum drm_exynos_ipp_buf_type {
- IPP_BUF_ENQUEUE,
- IPP_BUF_DEQUEUE,
+  IPP_BUF_ENQUEUE,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  IPP_BUF_DEQUEUE,
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_exynos_ipp_queue_buf {
- enum drm_exynos_ops_id ops_id;
- enum drm_exynos_ipp_buf_type buf_type;
- __u32 prop_id;
+  enum drm_exynos_ops_id ops_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 buf_id;
- __u32 handle[EXYNOS_DRM_PLANAR_MAX];
- __u32 reserved;
- __u64 user_data;
+  enum drm_exynos_ipp_buf_type buf_type;
+  __u32 prop_id;
+  __u32 buf_id;
+  __u32 handle[EXYNOS_DRM_PLANAR_MAX];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  __u32 reserved;
+  __u64 user_data;
 };
 enum drm_exynos_ipp_ctrl {
- IPP_CTRL_PLAY,
- IPP_CTRL_STOP,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- IPP_CTRL_PAUSE,
- IPP_CTRL_RESUME,
- IPP_CTRL_MAX,
+  IPP_CTRL_PLAY,
+  IPP_CTRL_STOP,
+  IPP_CTRL_PAUSE,
+  IPP_CTRL_RESUME,
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  IPP_CTRL_MAX,
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_exynos_ipp_cmd_ctrl {
- __u32 prop_id;
- enum drm_exynos_ipp_ctrl ctrl;
-};
+  __u32 prop_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  enum drm_exynos_ipp_ctrl ctrl;
+};
 #define DRM_EXYNOS_GEM_CREATE 0x00
 #define DRM_EXYNOS_GEM_GET 0x04
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_EXYNOS_VIDI_CONNECTION 0x07
 #define DRM_EXYNOS_G2D_GET_VER 0x20
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
 #define DRM_EXYNOS_G2D_EXEC 0x22
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33
-#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
-#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
-#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
-#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
-#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
+#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
+#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
+#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
+#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
-#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
-#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
-#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE +   DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
+#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
+#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
+#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
+#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
+#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
 #define DRM_EXYNOS_G2D_EVENT 0x80000000
 #define DRM_EXYNOS_IPP_EVENT 0x80000001
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_exynos_g2d_event {
- struct drm_event base;
+  struct drm_event base;
+  __u64 user_data;
+  __u32 tv_sec;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 user_data;
- __u32 tv_sec;
- __u32 tv_usec;
- __u32 cmdlist_no;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 reserved;
+  __u32 tv_usec;
+  __u32 cmdlist_no;
+  __u32 reserved;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_exynos_ipp_event {
- struct drm_event base;
+  struct drm_event base;
+  __u64 user_data;
+  __u32 tv_sec;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 user_data;
- __u32 tv_sec;
- __u32 tv_usec;
- __u32 prop_id;
+  __u32 tv_usec;
+  __u32 prop_id;
+  __u32 reserved;
+  __u32 buf_id[EXYNOS_DRM_OPS_MAX];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 reserved;
- __u32 buf_id[EXYNOS_DRM_OPS_MAX];
 };
 #endif
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
diff --git a/libc/kernel/uapi/drm/i810_drm.h b/libc/kernel/uapi/drm/i810_drm.h
index 946833d..ebe3332 100644
--- a/libc/kernel/uapi/drm/i810_drm.h
+++ b/libc/kernel/uapi/drm/i810_drm.h
@@ -22,7 +22,7 @@
 #define _I810_DEFINES_
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define I810_DMA_BUF_ORDER 12
-#define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER)
+#define I810_DMA_BUF_SZ (1 << I810_DMA_BUF_ORDER)
 #define I810_DMA_BUF_NR 256
 #define I810_NR_SAREA_CLIPRECTS 8
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -93,81 +93,81 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define I810_DEPTH 0x4
 typedef enum _drm_i810_init_func {
- I810_INIT_DMA = 0x01,
- I810_CLEANUP_DMA = 0x02,
+  I810_INIT_DMA = 0x01,
+  I810_CLEANUP_DMA = 0x02,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- I810_INIT_DMA_1_4 = 0x03
+  I810_INIT_DMA_1_4 = 0x03
 } drm_i810_init_func_t;
 typedef struct _drm_i810_init {
- drm_i810_init_func_t func;
+  drm_i810_init_func_t func;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int mmio_offset;
- unsigned int buffers_offset;
- int sarea_priv_offset;
- unsigned int ring_start;
+  unsigned int mmio_offset;
+  unsigned int buffers_offset;
+  int sarea_priv_offset;
+  unsigned int ring_start;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int ring_end;
- unsigned int ring_size;
- unsigned int front_offset;
- unsigned int back_offset;
+  unsigned int ring_end;
+  unsigned int ring_size;
+  unsigned int front_offset;
+  unsigned int back_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int depth_offset;
- unsigned int overlay_offset;
- unsigned int overlay_physical;
- unsigned int w;
+  unsigned int depth_offset;
+  unsigned int overlay_offset;
+  unsigned int overlay_physical;
+  unsigned int w;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int h;
- unsigned int pitch;
- unsigned int pitch_bits;
+  unsigned int h;
+  unsigned int pitch;
+  unsigned int pitch_bits;
 } drm_i810_init_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct _drm_i810_pre12_init {
- drm_i810_init_func_t func;
- unsigned int mmio_offset;
- unsigned int buffers_offset;
+  drm_i810_init_func_t func;
+  unsigned int mmio_offset;
+  unsigned int buffers_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int sarea_priv_offset;
- unsigned int ring_start;
- unsigned int ring_end;
- unsigned int ring_size;
+  int sarea_priv_offset;
+  unsigned int ring_start;
+  unsigned int ring_end;
+  unsigned int ring_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int front_offset;
- unsigned int back_offset;
- unsigned int depth_offset;
- unsigned int w;
+  unsigned int front_offset;
+  unsigned int back_offset;
+  unsigned int depth_offset;
+  unsigned int w;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int h;
- unsigned int pitch;
- unsigned int pitch_bits;
+  unsigned int h;
+  unsigned int pitch;
+  unsigned int pitch_bits;
 } drm_i810_pre12_init_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct _drm_i810_tex_region {
- unsigned char next, prev;
- unsigned char in_use;
- int age;
+  unsigned char next, prev;
+  unsigned char in_use;
+  int age;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_i810_tex_region_t;
 typedef struct _drm_i810_sarea {
- unsigned int ContextState[I810_CTX_SETUP_SIZE];
- unsigned int BufferState[I810_DEST_SETUP_SIZE];
+  unsigned int ContextState[I810_CTX_SETUP_SIZE];
+  unsigned int BufferState[I810_DEST_SETUP_SIZE];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int TexState[2][I810_TEX_SETUP_SIZE];
- unsigned int dirty;
- unsigned int nbox;
- struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
+  unsigned int TexState[2][I810_TEX_SETUP_SIZE];
+  unsigned int dirty;
+  unsigned int nbox;
+  struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
- int texAge;
- int last_enqueue;
- int last_dispatch;
+  drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
+  int texAge;
+  int last_enqueue;
+  int last_dispatch;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int last_quiescent;
- int ctxOwner;
- int vertex_prim;
- int pf_enabled;
+  int last_quiescent;
+  int ctxOwner;
+  int vertex_prim;
+  int pf_enabled;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int pf_active;
- int pf_current_page;
+  int pf_active;
+  int pf_current_page;
 } drm_i810_sarea_t;
 #define DRM_I810_INIT 0x00
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -188,74 +188,74 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_I810_RSTATUS 0x0d
 #define DRM_I810_FLIP 0x0e
-#define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
-#define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
+#define DRM_IOCTL_I810_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
+#define DRM_IOCTL_I810_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
-#define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH)
-#define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE)
+#define DRM_IOCTL_I810_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
+#define DRM_IOCTL_I810_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLUSH)
+#define DRM_IOCTL_I810_GETAGE DRM_IO(DRM_COMMAND_BASE + DRM_I810_GETAGE)
 #define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP)
-#define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
-#define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY)
-#define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
+#define DRM_IOCTL_I810_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_I810_SWAP)
+#define DRM_IOCTL_I810_COPY DRM_IOW(DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
+#define DRM_IOCTL_I810_DOCOPY DRM_IO(DRM_COMMAND_BASE + DRM_I810_DOCOPY)
+#define DRM_IOCTL_I810_OV0INFO DRM_IOR(DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
-#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
-#define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
-#define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
+#define DRM_IOCTL_I810_FSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_FSTATUS)
+#define DRM_IOCTL_I810_OV0FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
+#define DRM_IOCTL_I810_MC DRM_IOW(DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
+#define DRM_IOCTL_I810_RSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_RSTATUS)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
+#define DRM_IOCTL_I810_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLIP)
 typedef struct _drm_i810_clear {
- int clear_color;
- int clear_depth;
+  int clear_color;
+  int clear_depth;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int flags;
+  int flags;
 } drm_i810_clear_t;
 typedef struct _drm_i810_vertex {
- int idx;
+  int idx;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int used;
- int discard;
+  int used;
+  int discard;
 } drm_i810_vertex_t;
 typedef struct _drm_i810_copy_t {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int idx;
- int used;
- void *address;
+  int idx;
+  int used;
+  void * address;
 } drm_i810_copy_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PR_TRIANGLES (0x0<<18)
-#define PR_TRISTRIP_0 (0x1<<18)
-#define PR_TRISTRIP_1 (0x2<<18)
-#define PR_TRIFAN (0x3<<18)
+#define PR_TRIANGLES (0x0 << 18)
+#define PR_TRISTRIP_0 (0x1 << 18)
+#define PR_TRISTRIP_1 (0x2 << 18)
+#define PR_TRIFAN (0x3 << 18)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PR_POLYGON (0x4<<18)
-#define PR_LINES (0x5<<18)
-#define PR_LINESTRIP (0x6<<18)
-#define PR_RECTS (0x7<<18)
+#define PR_POLYGON (0x4 << 18)
+#define PR_LINES (0x5 << 18)
+#define PR_LINESTRIP (0x6 << 18)
+#define PR_RECTS (0x7 << 18)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define PR_MASK (0x7<<18)
+#define PR_MASK (0x7 << 18)
 typedef struct drm_i810_dma {
- void *virtual;
- int request_idx;
+  void * virtual;
+  int request_idx;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int request_size;
- int granted;
+  int request_size;
+  int granted;
 } drm_i810_dma_t;
 typedef struct _drm_i810_overlay_t {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int offset;
- unsigned int physical;
+  unsigned int offset;
+  unsigned int physical;
 } drm_i810_overlay_t;
 typedef struct _drm_i810_mc {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int idx;
- int used;
- int num_blocks;
- int *length;
+  int idx;
+  int used;
+  int num_blocks;
+  int * length;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int last_render;
+  unsigned int last_render;
 } drm_i810_mc_t;
 #endif
diff --git a/libc/kernel/uapi/drm/i915_drm.h b/libc/kernel/uapi/drm/i915_drm.h
index 3274ecf..3d15fec 100644
--- a/libc/kernel/uapi/drm/i915_drm.h
+++ b/libc/kernel/uapi/drm/i915_drm.h
@@ -27,96 +27,96 @@
 #define I915_LOG_MIN_TEX_REGION_SIZE 14
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct _drm_i915_init {
- enum {
- I915_INIT_DMA = 0x01,
- I915_CLEANUP_DMA = 0x02,
+  enum {
+    I915_INIT_DMA = 0x01,
+    I915_CLEANUP_DMA = 0x02,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- I915_RESUME_DMA = 0x03
- } func;
- unsigned int mmio_offset;
- int sarea_priv_offset;
+    I915_RESUME_DMA = 0x03
+  } func;
+  unsigned int mmio_offset;
+  int sarea_priv_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int ring_start;
- unsigned int ring_end;
- unsigned int ring_size;
- unsigned int front_offset;
+  unsigned int ring_start;
+  unsigned int ring_end;
+  unsigned int ring_size;
+  unsigned int front_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int back_offset;
- unsigned int depth_offset;
- unsigned int w;
- unsigned int h;
+  unsigned int back_offset;
+  unsigned int depth_offset;
+  unsigned int w;
+  unsigned int h;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int pitch;
- unsigned int pitch_bits;
- unsigned int back_pitch;
- unsigned int depth_pitch;
+  unsigned int pitch;
+  unsigned int pitch_bits;
+  unsigned int back_pitch;
+  unsigned int depth_pitch;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int cpp;
- unsigned int chipset;
+  unsigned int cpp;
+  unsigned int chipset;
 } drm_i915_init_t;
 typedef struct _drm_i915_sarea {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
- int last_upload;
- int last_enqueue;
- int last_dispatch;
+  struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
+  int last_upload;
+  int last_enqueue;
+  int last_dispatch;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int ctxOwner;
- int texAge;
- int pf_enabled;
- int pf_active;
+  int ctxOwner;
+  int texAge;
+  int pf_enabled;
+  int pf_active;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int pf_current_page;
- int perf_boxes;
- int width, height;
- drm_handle_t front_handle;
+  int pf_current_page;
+  int perf_boxes;
+  int width, height;
+  drm_handle_t front_handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int front_offset;
- int front_size;
- drm_handle_t back_handle;
- int back_offset;
+  int front_offset;
+  int front_size;
+  drm_handle_t back_handle;
+  int back_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int back_size;
- drm_handle_t depth_handle;
- int depth_offset;
- int depth_size;
+  int back_size;
+  drm_handle_t depth_handle;
+  int depth_offset;
+  int depth_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_handle_t tex_handle;
- int tex_offset;
- int tex_size;
- int log_tex_granularity;
+  drm_handle_t tex_handle;
+  int tex_offset;
+  int tex_size;
+  int log_tex_granularity;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int pitch;
- int rotation;
- int rotated_offset;
- int rotated_size;
+  int pitch;
+  int rotation;
+  int rotated_offset;
+  int rotated_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int rotated_pitch;
- int virtualX, virtualY;
- unsigned int front_tiled;
- unsigned int back_tiled;
+  int rotated_pitch;
+  int virtualX, virtualY;
+  unsigned int front_tiled;
+  unsigned int back_tiled;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int depth_tiled;
- unsigned int rotated_tiled;
- unsigned int rotated2_tiled;
- int pipeA_x;
+  unsigned int depth_tiled;
+  unsigned int rotated_tiled;
+  unsigned int rotated2_tiled;
+  int pipeA_x;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int pipeA_y;
- int pipeA_w;
- int pipeA_h;
- int pipeB_x;
+  int pipeA_y;
+  int pipeA_w;
+  int pipeA_h;
+  int pipeB_x;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int pipeB_y;
- int pipeB_w;
- int pipeB_h;
- drm_handle_t unused_handle;
+  int pipeB_y;
+  int pipeB_w;
+  int pipeB_h;
+  drm_handle_t unused_handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 unused1, unused2, unused3;
- __u32 front_bo_handle;
- __u32 back_bo_handle;
- __u32 unused_bo_handle;
+  __u32 unused1, unused2, unused3;
+  __u32 front_bo_handle;
+  __u32 back_bo_handle;
+  __u32 unused_bo_handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 depth_bo_handle;
+  __u32 depth_bo_handle;
 } drm_i915_sarea_t;
 #define planeA_x pipeA_x
 #define planeA_y pipeA_y
@@ -197,24 +197,24 @@
 #define DRM_I915_GET_RESET_STATS 0x32
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_I915_GEM_USERPTR 0x33
-#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
-#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
-#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
+#define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
+#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH)
+#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
+#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
-#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
+#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
+#define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
-#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
-#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
+#define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
+#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
-#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
-#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
-#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
+#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
+#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
+#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
+#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
@@ -228,22 +228,22 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
-#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
+#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
-#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
-#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
+#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
+#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
-#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
-#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
+#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
+#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
-#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
-#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
+#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
+#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
+#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
@@ -253,38 +253,38 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
-#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
-#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
-#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
-#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
+#define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
+#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
+#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
 typedef struct drm_i915_batchbuffer {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int start;
- int used;
- int DR1;
- int DR4;
+  int start;
+  int used;
+  int DR1;
+  int DR4;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int num_cliprects;
- struct drm_clip_rect __user *cliprects;
+  int num_cliprects;
+  struct drm_clip_rect __user * cliprects;
 } drm_i915_batchbuffer_t;
 typedef struct _drm_i915_cmdbuffer {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- char __user *buf;
- int sz;
- int DR1;
- int DR4;
+  char __user * buf;
+  int sz;
+  int DR1;
+  int DR4;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int num_cliprects;
- struct drm_clip_rect __user *cliprects;
+  int num_cliprects;
+  struct drm_clip_rect __user * cliprects;
 } drm_i915_cmdbuffer_t;
 typedef struct drm_i915_irq_emit {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int __user *irq_seq;
+  int __user * irq_seq;
 } drm_i915_irq_emit_t;
 typedef struct drm_i915_irq_wait {
- int irq_seq;
+  int irq_seq;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_i915_irq_wait_t;
 #define I915_PARAM_IRQ_ACTIVE 1
@@ -323,8 +323,8 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define I915_PARAM_CMD_PARSER_VERSION 28
 typedef struct drm_i915_getparam {
- int param;
- int __user *value;
+  int param;
+  int __user * value;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_i915_getparam_t;
 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
@@ -333,112 +333,112 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define I915_SETPARAM_NUM_USED_FENCES 4
 typedef struct drm_i915_setparam {
- int param;
- int value;
+  int param;
+  int value;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_i915_setparam_t;
 #define I915_MEM_REGION_AGP 1
 typedef struct drm_i915_mem_alloc {
- int region;
+  int region;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int alignment;
- int size;
- int __user *region_offset;
+  int alignment;
+  int size;
+  int __user * region_offset;
 } drm_i915_mem_alloc_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_i915_mem_free {
- int region;
- int region_offset;
+  int region;
+  int region_offset;
 } drm_i915_mem_free_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_i915_mem_init_heap {
- int region;
- int size;
- int start;
+  int region;
+  int size;
+  int start;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_i915_mem_init_heap_t;
 typedef struct drm_i915_mem_destroy_heap {
- int region;
+  int region;
 } drm_i915_mem_destroy_heap_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_I915_VBLANK_PIPE_A 1
 #define DRM_I915_VBLANK_PIPE_B 2
 typedef struct drm_i915_vblank_pipe {
- int pipe;
+  int pipe;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_i915_vblank_pipe_t;
 typedef struct drm_i915_vblank_swap {
- drm_drawable_t drawable;
- enum drm_vblank_seq_type seqtype;
+  drm_drawable_t drawable;
+  enum drm_vblank_seq_type seqtype;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int sequence;
+  unsigned int sequence;
 } drm_i915_vblank_swap_t;
 typedef struct drm_i915_hws_addr {
- __u64 addr;
+  __u64 addr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_i915_hws_addr_t;
 struct drm_i915_gem_init {
- __u64 gtt_start;
- __u64 gtt_end;
+  __u64 gtt_start;
+  __u64 gtt_end;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_i915_gem_create {
- __u64 size;
- __u32 handle;
+  __u64 size;
+  __u32 handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 pad;
+  __u32 pad;
 };
 struct drm_i915_gem_pread {
- __u32 handle;
+  __u32 handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 pad;
- __u64 offset;
- __u64 size;
- __u64 data_ptr;
+  __u32 pad;
+  __u64 offset;
+  __u64 size;
+  __u64 data_ptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_i915_gem_pwrite {
- __u32 handle;
- __u32 pad;
+  __u32 handle;
+  __u32 pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 offset;
- __u64 size;
- __u64 data_ptr;
+  __u64 offset;
+  __u64 size;
+  __u64 data_ptr;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_mmap {
- __u32 handle;
- __u32 pad;
- __u64 offset;
+  __u32 handle;
+  __u32 pad;
+  __u64 offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 size;
- __u64 addr_ptr;
+  __u64 size;
+  __u64 addr_ptr;
 };
 struct drm_i915_gem_mmap_gtt {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
- __u32 pad;
- __u64 offset;
+  __u32 handle;
+  __u32 pad;
+  __u64 offset;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_set_domain {
- __u32 handle;
- __u32 read_domains;
- __u32 write_domain;
+  __u32 handle;
+  __u32 read_domains;
+  __u32 write_domain;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_i915_gem_sw_finish {
- __u32 handle;
+  __u32 handle;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_relocation_entry {
- __u32 target_handle;
- __u32 delta;
- __u64 offset;
+  __u32 target_handle;
+  __u32 delta;
+  __u64 offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 presumed_offset;
- __u32 read_domains;
- __u32 write_domain;
+  __u64 presumed_offset;
+  __u32 read_domains;
+  __u32 write_domain;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define I915_GEM_DOMAIN_CPU 0x00000001
@@ -451,99 +451,99 @@
 #define I915_GEM_DOMAIN_GTT 0x00000040
 struct drm_i915_gem_exec_object {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
- __u32 relocation_count;
- __u64 relocs_ptr;
- __u64 alignment;
+  __u32 handle;
+  __u32 relocation_count;
+  __u64 relocs_ptr;
+  __u64 alignment;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 offset;
+  __u64 offset;
 };
 struct drm_i915_gem_execbuffer {
- __u64 buffers_ptr;
+  __u64 buffers_ptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 buffer_count;
- __u32 batch_start_offset;
- __u32 batch_len;
- __u32 DR1;
+  __u32 buffer_count;
+  __u32 batch_start_offset;
+  __u32 batch_len;
+  __u32 DR1;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 DR4;
- __u32 num_cliprects;
- __u64 cliprects_ptr;
+  __u32 DR4;
+  __u32 num_cliprects;
+  __u64 cliprects_ptr;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_exec_object2 {
- __u32 handle;
- __u32 relocation_count;
- __u64 relocs_ptr;
+  __u32 handle;
+  __u32 relocation_count;
+  __u64 relocs_ptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 alignment;
- __u64 offset;
-#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
-#define EXEC_OBJECT_NEEDS_GTT (1<<1)
+  __u64 alignment;
+  __u64 offset;
+#define EXEC_OBJECT_NEEDS_FENCE (1 << 0)
+#define EXEC_OBJECT_NEEDS_GTT (1 << 1)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define EXEC_OBJECT_WRITE (1<<2)
-#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
- __u64 flags;
- __u64 rsvd1;
+#define EXEC_OBJECT_WRITE (1 << 2)
+#define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_WRITE << 1)
+  __u64 flags;
+  __u64 rsvd1;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 rsvd2;
+  __u64 rsvd2;
 };
 struct drm_i915_gem_execbuffer2 {
- __u64 buffers_ptr;
+  __u64 buffers_ptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 buffer_count;
- __u32 batch_start_offset;
- __u32 batch_len;
- __u32 DR1;
+  __u32 buffer_count;
+  __u32 batch_start_offset;
+  __u32 batch_len;
+  __u32 DR1;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 DR4;
- __u32 num_cliprects;
- __u64 cliprects_ptr;
-#define I915_EXEC_RING_MASK (7<<0)
+  __u32 DR4;
+  __u32 num_cliprects;
+  __u64 cliprects_ptr;
+#define I915_EXEC_RING_MASK (7 << 0)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define I915_EXEC_DEFAULT (0<<0)
-#define I915_EXEC_RENDER (1<<0)
-#define I915_EXEC_BSD (2<<0)
-#define I915_EXEC_BLT (3<<0)
+#define I915_EXEC_DEFAULT (0 << 0)
+#define I915_EXEC_RENDER (1 << 0)
+#define I915_EXEC_BSD (2 << 0)
+#define I915_EXEC_BLT (3 << 0)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define I915_EXEC_VEBOX (4<<0)
-#define I915_EXEC_CONSTANTS_MASK (3<<6)
-#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6)
-#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
+#define I915_EXEC_VEBOX (4 << 0)
+#define I915_EXEC_CONSTANTS_MASK (3 << 6)
+#define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6)
+#define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6)
- __u64 flags;
- __u64 rsvd1;
- __u64 rsvd2;
+#define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6)
+  __u64 flags;
+  __u64 rsvd1;
+  __u64 rsvd2;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
-#define I915_EXEC_GEN7_SOL_RESET (1<<8)
-#define I915_EXEC_SECURE (1<<9)
-#define I915_EXEC_IS_PINNED (1<<10)
+#define I915_EXEC_GEN7_SOL_RESET (1 << 8)
+#define I915_EXEC_SECURE (1 << 9)
+#define I915_EXEC_IS_PINNED (1 << 10)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define I915_EXEC_NO_RELOC (1<<11)
-#define I915_EXEC_HANDLE_LUT (1<<12)
-#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
+#define I915_EXEC_NO_RELOC (1 << 11)
+#define I915_EXEC_HANDLE_LUT (1 << 12)
+#define __I915_EXEC_UNKNOWN_FLAGS - (I915_EXEC_HANDLE_LUT << 1)
 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define i915_execbuffer2_set_context_id(eb2, context)   (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
-#define i915_execbuffer2_get_context_id(eb2)   ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
+#define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
+#define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
 struct drm_i915_gem_pin {
- __u32 handle;
+  __u32 handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 pad;
- __u64 alignment;
- __u64 offset;
+  __u32 pad;
+  __u64 alignment;
+  __u64 offset;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_unpin {
- __u32 handle;
- __u32 pad;
+  __u32 handle;
+  __u32 pad;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_busy {
- __u32 handle;
- __u32 busy;
+  __u32 handle;
+  __u32 busy;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define I915_CACHING_NONE 0
@@ -551,8 +551,8 @@
 #define I915_CACHING_DISPLAY 2
 struct drm_i915_gem_caching {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
- __u32 caching;
+  __u32 handle;
+  __u32 caching;
 };
 #define I915_TILING_NONE 0
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -569,27 +569,27 @@
 #define I915_BIT_6_SWIZZLE_9_17 6
 #define I915_BIT_6_SWIZZLE_9_10_17 7
 struct drm_i915_gem_set_tiling {
- __u32 handle;
+  __u32 handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 tiling_mode;
- __u32 stride;
- __u32 swizzle_mode;
+  __u32 tiling_mode;
+  __u32 stride;
+  __u32 swizzle_mode;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_get_tiling {
- __u32 handle;
- __u32 tiling_mode;
- __u32 swizzle_mode;
+  __u32 handle;
+  __u32 tiling_mode;
+  __u32 swizzle_mode;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_i915_gem_get_aperture {
- __u64 aper_size;
- __u64 aper_available_size;
+  __u64 aper_size;
+  __u64 aper_available_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_i915_get_pipe_from_crtc_id {
- __u32 crtc_id;
- __u32 pipe;
+  __u32 crtc_id;
+  __u32 pipe;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define I915_MADV_WILLNEED 0
@@ -597,9 +597,9 @@
 #define __I915_MADV_PURGED 2
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_madvise {
- __u32 handle;
- __u32 madv;
- __u32 retained;
+  __u32 handle;
+  __u32 madv;
+  __u32 retained;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define I915_OVERLAY_TYPE_MASK 0xff
@@ -627,98 +627,98 @@
 #define I915_OVERLAY_ENABLE 0x01000000
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_intel_overlay_put_image {
- __u32 flags;
- __u32 bo_handle;
- __u16 stride_Y;
+  __u32 flags;
+  __u32 bo_handle;
+  __u16 stride_Y;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u16 stride_UV;
- __u32 offset_Y;
- __u32 offset_U;
- __u32 offset_V;
+  __u16 stride_UV;
+  __u32 offset_Y;
+  __u32 offset_U;
+  __u32 offset_V;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u16 src_width;
- __u16 src_height;
- __u16 src_scan_width;
- __u16 src_scan_height;
+  __u16 src_width;
+  __u16 src_height;
+  __u16 src_scan_width;
+  __u16 src_scan_height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 crtc_id;
- __u16 dst_x;
- __u16 dst_y;
- __u16 dst_width;
+  __u32 crtc_id;
+  __u16 dst_x;
+  __u16 dst_y;
+  __u16 dst_width;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u16 dst_height;
+  __u16 dst_height;
 };
-#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
-#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
+#define I915_OVERLAY_UPDATE_ATTRS (1 << 0)
+#define I915_OVERLAY_UPDATE_GAMMA (1 << 1)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_intel_overlay_attrs {
- __u32 flags;
- __u32 color_key;
- __s32 brightness;
+  __u32 flags;
+  __u32 color_key;
+  __s32 brightness;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 contrast;
- __u32 saturation;
- __u32 gamma0;
- __u32 gamma1;
+  __u32 contrast;
+  __u32 saturation;
+  __u32 gamma0;
+  __u32 gamma1;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 gamma2;
- __u32 gamma3;
- __u32 gamma4;
- __u32 gamma5;
+  __u32 gamma2;
+  __u32 gamma3;
+  __u32 gamma4;
+  __u32 gamma5;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
-#define I915_SET_COLORKEY_NONE (1<<0)
-#define I915_SET_COLORKEY_DESTINATION (1<<1)
-#define I915_SET_COLORKEY_SOURCE (1<<2)
+#define I915_SET_COLORKEY_NONE (1 << 0)
+#define I915_SET_COLORKEY_DESTINATION (1 << 1)
+#define I915_SET_COLORKEY_SOURCE (1 << 2)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_intel_sprite_colorkey {
- __u32 plane_id;
- __u32 min_value;
- __u32 channel_mask;
+  __u32 plane_id;
+  __u32 min_value;
+  __u32 channel_mask;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 max_value;
- __u32 flags;
+  __u32 max_value;
+  __u32 flags;
 };
 struct drm_i915_gem_wait {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 bo_handle;
- __u32 flags;
- __s64 timeout_ns;
+  __u32 bo_handle;
+  __u32 flags;
+  __s64 timeout_ns;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_context_create {
- __u32 ctx_id;
- __u32 pad;
+  __u32 ctx_id;
+  __u32 pad;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_context_destroy {
- __u32 ctx_id;
- __u32 pad;
+  __u32 ctx_id;
+  __u32 pad;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_reg_read {
- __u64 offset;
- __u64 val;
+  __u64 offset;
+  __u64 val;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_reset_stats {
- __u32 ctx_id;
- __u32 flags;
- __u32 reset_count;
+  __u32 ctx_id;
+  __u32 flags;
+  __u32 reset_count;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 batch_active;
- __u32 batch_pending;
- __u32 pad;
+  __u32 batch_active;
+  __u32 batch_pending;
+  __u32 pad;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_i915_gem_userptr {
- __u64 user_ptr;
- __u64 user_size;
- __u32 flags;
+  __u64 user_ptr;
+  __u64 user_size;
+  __u32 flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define I915_USERPTR_READ_ONLY 0x1
 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
- __u32 handle;
+  __u32 handle;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
diff --git a/libc/kernel/uapi/drm/mga_drm.h b/libc/kernel/uapi/drm/mga_drm.h
index 8e43e4d..ded4d89 100644
--- a/libc/kernel/uapi/drm/mga_drm.h
+++ b/libc/kernel/uapi/drm/mga_drm.h
@@ -31,22 +31,22 @@
 #define MGA_WARP_TGZF (MGA_F)
 #define MGA_WARP_TGZA (MGA_A)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MGA_WARP_TGZAF (MGA_F|MGA_A)
+#define MGA_WARP_TGZAF (MGA_F | MGA_A)
 #define MGA_WARP_TGZS (MGA_S)
-#define MGA_WARP_TGZSF (MGA_S|MGA_F)
-#define MGA_WARP_TGZSA (MGA_S|MGA_A)
+#define MGA_WARP_TGZSF (MGA_S | MGA_F)
+#define MGA_WARP_TGZSA (MGA_S | MGA_A)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
+#define MGA_WARP_TGZSAF (MGA_S | MGA_F | MGA_A)
 #define MGA_WARP_T2GZ (MGA_T2)
-#define MGA_WARP_T2GZF (MGA_T2|MGA_F)
-#define MGA_WARP_T2GZA (MGA_T2|MGA_A)
+#define MGA_WARP_T2GZF (MGA_T2 | MGA_F)
+#define MGA_WARP_T2GZA (MGA_T2 | MGA_A)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
-#define MGA_WARP_T2GZS (MGA_T2|MGA_S)
-#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
-#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
+#define MGA_WARP_T2GZAF (MGA_T2 | MGA_A | MGA_F)
+#define MGA_WARP_T2GZS (MGA_T2 | MGA_S)
+#define MGA_WARP_T2GZSF (MGA_T2 | MGA_S | MGA_F)
+#define MGA_WARP_T2GZSA (MGA_T2 | MGA_S | MGA_A)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
+#define MGA_WARP_T2GZSAF (MGA_T2 | MGA_S | MGA_F | MGA_A)
 #define MGA_MAX_G200_PIPES 8
 #define MGA_MAX_G400_PIPES 16
 #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
@@ -86,83 +86,83 @@
 #endif
 typedef struct {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int dstorg;
- unsigned int maccess;
- unsigned int plnwt;
- unsigned int dwgctl;
+  unsigned int dstorg;
+  unsigned int maccess;
+  unsigned int plnwt;
+  unsigned int dwgctl;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int alphactrl;
- unsigned int fogcolor;
- unsigned int wflag;
- unsigned int tdualstage0;
+  unsigned int alphactrl;
+  unsigned int fogcolor;
+  unsigned int wflag;
+  unsigned int tdualstage0;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int tdualstage1;
- unsigned int fcol;
- unsigned int stencil;
- unsigned int stencilctl;
+  unsigned int tdualstage1;
+  unsigned int fcol;
+  unsigned int stencil;
+  unsigned int stencilctl;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_mga_context_regs_t;
 typedef struct {
- unsigned int pitch;
+  unsigned int pitch;
 } drm_mga_server_regs_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct {
- unsigned int texctl;
- unsigned int texctl2;
- unsigned int texfilter;
+  unsigned int texctl;
+  unsigned int texctl2;
+  unsigned int texfilter;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int texbordercol;
- unsigned int texorg;
- unsigned int texwidth;
- unsigned int texheight;
+  unsigned int texbordercol;
+  unsigned int texorg;
+  unsigned int texwidth;
+  unsigned int texheight;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int texorg1;
- unsigned int texorg2;
- unsigned int texorg3;
- unsigned int texorg4;
+  unsigned int texorg1;
+  unsigned int texorg2;
+  unsigned int texorg3;
+  unsigned int texorg4;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_mga_texture_regs_t;
 typedef struct {
- unsigned int head;
- unsigned int wrap;
+  unsigned int head;
+  unsigned int wrap;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_mga_age_t;
 typedef struct _drm_mga_sarea {
- drm_mga_context_regs_t context_state;
- drm_mga_server_regs_t server_state;
+  drm_mga_context_regs_t context_state;
+  drm_mga_server_regs_t server_state;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_mga_texture_regs_t tex_state[2];
- unsigned int warp_pipe;
- unsigned int dirty;
- unsigned int vertsize;
+  drm_mga_texture_regs_t tex_state[2];
+  unsigned int warp_pipe;
+  unsigned int dirty;
+  unsigned int vertsize;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
- unsigned int nbox;
- unsigned int req_drawable;
- unsigned int req_draw_buffer;
+  struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
+  unsigned int nbox;
+  unsigned int req_drawable;
+  unsigned int req_draw_buffer;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int exported_drawable;
- unsigned int exported_index;
- unsigned int exported_stamp;
- unsigned int exported_buffers;
+  unsigned int exported_drawable;
+  unsigned int exported_index;
+  unsigned int exported_stamp;
+  unsigned int exported_buffers;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int exported_nfront;
- unsigned int exported_nback;
- int exported_back_x, exported_front_x, exported_w;
- int exported_back_y, exported_front_y, exported_h;
+  unsigned int exported_nfront;
+  unsigned int exported_nback;
+  int exported_back_x, exported_front_x, exported_w;
+  int exported_back_y, exported_front_y, exported_h;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
- unsigned int status[4];
- unsigned int last_wrap;
- drm_mga_age_t last_frame;
+  struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
+  unsigned int status[4];
+  unsigned int last_wrap;
+  drm_mga_age_t last_frame;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int last_enqueue;
- unsigned int last_dispatch;
- unsigned int last_quiescent;
- struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
+  unsigned int last_enqueue;
+  unsigned int last_dispatch;
+  unsigned int last_quiescent;
+  struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int texAge[MGA_NR_TEX_HEAPS];
- int ctxOwner;
+  unsigned int texAge[MGA_NR_TEX_HEAPS];
+  int ctxOwner;
 } drm_mga_sarea_t;
 #define DRM_MGA_INIT 0x00
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -181,115 +181,115 @@
 #define DRM_MGA_WAIT_FENCE 0x0b
 #define DRM_MGA_DMA_BOOTSTRAP 0x0c
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
-#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
-#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
-#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
+#define DRM_IOCTL_MGA_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
+#define DRM_IOCTL_MGA_FLUSH DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
+#define DRM_IOCTL_MGA_RESET DRM_IO(DRM_COMMAND_BASE + DRM_MGA_RESET)
+#define DRM_IOCTL_MGA_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_MGA_SWAP)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
-#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
-#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
-#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
+#define DRM_IOCTL_MGA_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
+#define DRM_IOCTL_MGA_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
+#define DRM_IOCTL_MGA_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
+#define DRM_IOCTL_MGA_ILOAD DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
+#define DRM_IOCTL_MGA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
 #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
-#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
+#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
 #define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
 typedef struct _drm_mga_warp_index {
- int installed;
- unsigned long phys_addr;
+  int installed;
+  unsigned long phys_addr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int size;
+  int size;
 } drm_mga_warp_index_t;
 typedef struct drm_mga_init {
- enum {
+  enum {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- MGA_INIT_DMA = 0x01,
- MGA_CLEANUP_DMA = 0x02
- } func;
- unsigned long sarea_priv_offset;
+    MGA_INIT_DMA = 0x01,
+    MGA_CLEANUP_DMA = 0x02
+  } func;
+  unsigned long sarea_priv_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int chipset;
- int sgram;
- unsigned int maccess;
- unsigned int fb_cpp;
+  int chipset;
+  int sgram;
+  unsigned int maccess;
+  unsigned int fb_cpp;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int front_offset, front_pitch;
- unsigned int back_offset, back_pitch;
- unsigned int depth_cpp;
- unsigned int depth_offset, depth_pitch;
+  unsigned int front_offset, front_pitch;
+  unsigned int back_offset, back_pitch;
+  unsigned int depth_cpp;
+  unsigned int depth_offset, depth_pitch;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int texture_offset[MGA_NR_TEX_HEAPS];
- unsigned int texture_size[MGA_NR_TEX_HEAPS];
- unsigned long fb_offset;
- unsigned long mmio_offset;
+  unsigned int texture_offset[MGA_NR_TEX_HEAPS];
+  unsigned int texture_size[MGA_NR_TEX_HEAPS];
+  unsigned long fb_offset;
+  unsigned long mmio_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long status_offset;
- unsigned long warp_offset;
- unsigned long primary_offset;
- unsigned long buffers_offset;
+  unsigned long status_offset;
+  unsigned long warp_offset;
+  unsigned long primary_offset;
+  unsigned long buffers_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_mga_init_t;
 typedef struct drm_mga_dma_bootstrap {
- unsigned long texture_handle;
- __u32 texture_size;
+  unsigned long texture_handle;
+  __u32 texture_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 primary_size;
- __u32 secondary_bin_count;
- __u32 secondary_bin_size;
- __u32 agp_mode;
+  __u32 primary_size;
+  __u32 secondary_bin_count;
+  __u32 secondary_bin_size;
+  __u32 agp_mode;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u8 agp_size;
+  __u8 agp_size;
 } drm_mga_dma_bootstrap_t;
 typedef struct drm_mga_clear {
- unsigned int flags;
+  unsigned int flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int clear_color;
- unsigned int clear_depth;
- unsigned int color_mask;
- unsigned int depth_mask;
+  unsigned int clear_color;
+  unsigned int clear_depth;
+  unsigned int color_mask;
+  unsigned int depth_mask;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_mga_clear_t;
 typedef struct drm_mga_vertex {
- int idx;
- int used;
+  int idx;
+  int used;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int discard;
+  int discard;
 } drm_mga_vertex_t;
 typedef struct drm_mga_indices {
- int idx;
+  int idx;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int start;
- unsigned int end;
- int discard;
+  unsigned int start;
+  unsigned int end;
+  int discard;
 } drm_mga_indices_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_mga_iload {
- int idx;
- unsigned int dstorg;
- unsigned int length;
+  int idx;
+  unsigned int dstorg;
+  unsigned int length;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_mga_iload_t;
 typedef struct _drm_mga_blit {
- unsigned int planemask;
- unsigned int srcorg;
+  unsigned int planemask;
+  unsigned int srcorg;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int dstorg;
- int src_pitch, dst_pitch;
- int delta_sx, delta_sy;
- int delta_dx, delta_dy;
+  unsigned int dstorg;
+  int src_pitch, dst_pitch;
+  int delta_sx, delta_sy;
+  int delta_dx, delta_dy;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int height, ydir;
- int source_pitch, dest_pitch;
+  int height, ydir;
+  int source_pitch, dest_pitch;
 } drm_mga_blit_t;
 #define MGA_PARAM_IRQ_NR 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MGA_PARAM_CARD_TYPE 2
 typedef struct drm_mga_getparam {
- int param;
- void __user *value;
+  int param;
+  void __user * value;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_mga_getparam_t;
 #endif
diff --git a/libc/kernel/uapi/drm/msm_drm.h b/libc/kernel/uapi/drm/msm_drm.h
index 54257a7..8db4b0d 100644
--- a/libc/kernel/uapi/drm/msm_drm.h
+++ b/libc/kernel/uapi/drm/msm_drm.h
@@ -27,8 +27,8 @@
 #define MSM_PIPE_3D0 0x10
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_msm_timespec {
- int64_t tv_sec;
- int64_t tv_nsec;
+  int64_t tv_sec;
+  int64_t tv_nsec;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_PARAM_GPU_ID 0x01
@@ -36,9 +36,9 @@
 #define MSM_PARAM_CHIP_ID 0x03
 struct drm_msm_param {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pipe;
- uint32_t param;
- uint64_t value;
+  uint32_t pipe;
+  uint32_t param;
+  uint64_t value;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_BO_SCANOUT 0x00000001
@@ -48,18 +48,18 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_BO_WC 0x00020000
 #define MSM_BO_UNCACHED 0x00040000
-#define MSM_BO_FLAGS (MSM_BO_SCANOUT |   MSM_BO_GPU_READONLY |   MSM_BO_CACHED |   MSM_BO_WC |   MSM_BO_UNCACHED)
+#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED)
 struct drm_msm_gem_new {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t size;
- uint32_t flags;
- uint32_t handle;
+  uint64_t size;
+  uint32_t flags;
+  uint32_t handle;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_msm_gem_info {
- uint32_t handle;
- uint32_t pad;
- uint64_t offset;
+  uint32_t handle;
+  uint32_t pad;
+  uint64_t offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define MSM_PREP_READ 0x01
@@ -68,22 +68,22 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
 struct drm_msm_gem_cpu_prep {
- uint32_t handle;
- uint32_t op;
+  uint32_t handle;
+  uint32_t op;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_msm_timespec timeout;
+  struct drm_msm_timespec timeout;
 };
 struct drm_msm_gem_cpu_fini {
- uint32_t handle;
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_msm_gem_submit_reloc {
- uint32_t submit_offset;
- uint32_t or;
+  uint32_t submit_offset;
+  uint32_t or;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int32_t shift;
- uint32_t reloc_idx;
- uint64_t reloc_offset;
+  int32_t shift;
+  uint32_t reloc_idx;
+  uint64_t reloc_offset;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_SUBMIT_CMD_BUF 0x0001
@@ -91,14 +91,14 @@
 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
 struct drm_msm_gem_submit_cmd {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t type;
- uint32_t submit_idx;
- uint32_t submit_offset;
- uint32_t size;
+  uint32_t type;
+  uint32_t submit_idx;
+  uint32_t submit_offset;
+  uint32_t size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pad;
- uint32_t nr_relocs;
- uint64_t __user relocs;
+  uint32_t pad;
+  uint32_t nr_relocs;
+  uint64_t __user relocs;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define MSM_SUBMIT_BO_READ 0x0001
@@ -106,25 +106,25 @@
 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
 struct drm_msm_gem_submit_bo {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t flags;
- uint32_t handle;
- uint64_t presumed;
+  uint32_t flags;
+  uint32_t handle;
+  uint64_t presumed;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_msm_gem_submit {
- uint32_t pipe;
- uint32_t fence;
- uint32_t nr_bos;
+  uint32_t pipe;
+  uint32_t fence;
+  uint32_t nr_bos;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t nr_cmds;
- uint64_t __user bos;
- uint64_t __user cmds;
+  uint32_t nr_cmds;
+  uint64_t __user bos;
+  uint64_t __user cmds;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_msm_wait_fence {
- uint32_t fence;
- uint32_t pad;
- struct drm_msm_timespec timeout;
+  uint32_t fence;
+  uint32_t pad;
+  struct drm_msm_timespec timeout;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define DRM_MSM_GET_PARAM 0x00
@@ -141,9 +141,9 @@
 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
-#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
+#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
+#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
-#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
+#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
diff --git a/libc/kernel/uapi/drm/nouveau_drm.h b/libc/kernel/uapi/drm/nouveau_drm.h
index d6d470f..29248a0 100644
--- a/libc/kernel/uapi/drm/nouveau_drm.h
+++ b/libc/kernel/uapi/drm/nouveau_drm.h
@@ -37,38 +37,38 @@
 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_nouveau_gem_info {
- uint32_t handle;
- uint32_t domain;
- uint64_t size;
+  uint32_t handle;
+  uint32_t domain;
+  uint64_t size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t offset;
- uint64_t map_handle;
- uint32_t tile_mode;
- uint32_t tile_flags;
+  uint64_t offset;
+  uint64_t map_handle;
+  uint32_t tile_mode;
+  uint32_t tile_flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_nouveau_gem_new {
- struct drm_nouveau_gem_info info;
- uint32_t channel_hint;
+  struct drm_nouveau_gem_info info;
+  uint32_t channel_hint;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t align;
+  uint32_t align;
 };
 #define NOUVEAU_GEM_MAX_BUFFERS 1024
 struct drm_nouveau_gem_pushbuf_bo_presumed {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t valid;
- uint32_t domain;
- uint64_t offset;
+  uint32_t valid;
+  uint32_t domain;
+  uint64_t offset;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_nouveau_gem_pushbuf_bo {
- uint64_t user_priv;
- uint32_t handle;
- uint32_t read_domains;
+  uint64_t user_priv;
+  uint32_t handle;
+  uint32_t read_domains;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t write_domains;
- uint32_t valid_domains;
- struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
+  uint32_t write_domains;
+  uint32_t valid_domains;
+  struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
@@ -77,51 +77,51 @@
 #define NOUVEAU_GEM_MAX_RELOCS 1024
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_nouveau_gem_pushbuf_reloc {
- uint32_t reloc_bo_index;
- uint32_t reloc_bo_offset;
- uint32_t bo_index;
+  uint32_t reloc_bo_index;
+  uint32_t reloc_bo_offset;
+  uint32_t bo_index;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t flags;
- uint32_t data;
- uint32_t vor;
- uint32_t tor;
+  uint32_t flags;
+  uint32_t data;
+  uint32_t vor;
+  uint32_t tor;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define NOUVEAU_GEM_MAX_PUSH 512
 struct drm_nouveau_gem_pushbuf_push {
- uint32_t bo_index;
+  uint32_t bo_index;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pad;
- uint64_t offset;
- uint64_t length;
+  uint32_t pad;
+  uint64_t offset;
+  uint64_t length;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_nouveau_gem_pushbuf {
- uint32_t channel;
- uint32_t nr_buffers;
- uint64_t buffers;
+  uint32_t channel;
+  uint32_t nr_buffers;
+  uint64_t buffers;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t nr_relocs;
- uint32_t nr_push;
- uint64_t relocs;
- uint64_t push;
+  uint32_t nr_relocs;
+  uint32_t nr_push;
+  uint64_t relocs;
+  uint64_t push;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t suffix0;
- uint32_t suffix1;
- uint64_t vram_available;
- uint64_t gart_available;
+  uint32_t suffix0;
+  uint32_t suffix1;
+  uint64_t vram_available;
+  uint64_t gart_available;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
 struct drm_nouveau_gem_cpu_prep {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t flags;
+  uint32_t handle;
+  uint32_t flags;
 };
 struct drm_nouveau_gem_cpu_fini {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
+  uint32_t handle;
 };
 #define DRM_NOUVEAU_GETPARAM 0x00
 #define DRM_NOUVEAU_SETPARAM 0x01
@@ -142,8 +142,8 @@
 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
-#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
-#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
+#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
+#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
diff --git a/libc/kernel/uapi/drm/omap_drm.h b/libc/kernel/uapi/drm/omap_drm.h
index 2d4cb53..efca002 100644
--- a/libc/kernel/uapi/drm/omap_drm.h
+++ b/libc/kernel/uapi/drm/omap_drm.h
@@ -22,8 +22,8 @@
 #define OMAP_PARAM_CHIPSET_ID 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_omap_param {
- uint64_t param;
- uint64_t value;
+  uint64_t param;
+  uint64_t value;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define OMAP_BO_SCANOUT 0x00000001
@@ -39,46 +39,46 @@
 #define OMAP_BO_TILED_32 0x00000300
 #define OMAP_BO_TILED (OMAP_BO_TILED_8 | OMAP_BO_TILED_16 | OMAP_BO_TILED_32)
 union omap_gem_size {
- uint32_t bytes;
+  uint32_t bytes;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct {
- uint16_t width;
- uint16_t height;
- } tiled;
+  struct {
+    uint16_t width;
+    uint16_t height;
+  } tiled;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_omap_gem_new {
- union omap_gem_size size;
- uint32_t flags;
+  union omap_gem_size size;
+  uint32_t flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t __pad;
+  uint32_t handle;
+  uint32_t __pad;
 };
 enum omap_gem_op {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- OMAP_GEM_READ = 0x01,
- OMAP_GEM_WRITE = 0x02,
+  OMAP_GEM_READ = 0x01,
+  OMAP_GEM_WRITE = 0x02,
 };
 struct drm_omap_gem_cpu_prep {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t op;
+  uint32_t handle;
+  uint32_t op;
 };
 struct drm_omap_gem_cpu_fini {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t op;
- uint32_t nregions;
- uint32_t __pad;
+  uint32_t handle;
+  uint32_t op;
+  uint32_t nregions;
+  uint32_t __pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_omap_gem_info {
- uint32_t handle;
- uint32_t pad;
+  uint32_t handle;
+  uint32_t pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t offset;
- uint32_t size;
- uint32_t __pad;
+  uint64_t offset;
+  uint32_t size;
+  uint32_t __pad;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_OMAP_GET_PARAM 0x00
@@ -91,10 +91,10 @@
 #define DRM_OMAP_NUM_IOCTLS 0x07
 #define DRM_IOCTL_OMAP_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_PARAM, struct drm_omap_param)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_OMAP_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_SET_PARAM, struct drm_omap_param)
+#define DRM_IOCTL_OMAP_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_OMAP_SET_PARAM, struct drm_omap_param)
 #define DRM_IOCTL_OMAP_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_NEW, struct drm_omap_gem_new)
-#define DRM_IOCTL_OMAP_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_PREP, struct drm_omap_gem_cpu_prep)
-#define DRM_IOCTL_OMAP_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini)
+#define DRM_IOCTL_OMAP_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_PREP, struct drm_omap_gem_cpu_prep)
+#define DRM_IOCTL_OMAP_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_OMAP_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_INFO, struct drm_omap_gem_info)
 #endif
diff --git a/libc/kernel/uapi/drm/qxl_drm.h b/libc/kernel/uapi/drm/qxl_drm.h
index 4f48668..3878b75 100644
--- a/libc/kernel/uapi/drm/qxl_drm.h
+++ b/libc/kernel/uapi/drm/qxl_drm.h
@@ -34,85 +34,85 @@
 #define DRM_QXL_CLIENTCAP 0x05
 #define DRM_QXL_ALLOC_SURF 0x06
 struct drm_qxl_alloc {
- uint32_t size;
+  uint32_t size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
+  uint32_t handle;
 };
 struct drm_qxl_map {
- uint64_t offset;
+  uint64_t offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t pad;
+  uint32_t handle;
+  uint32_t pad;
 };
 #define QXL_RELOC_TYPE_BO 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define QXL_RELOC_TYPE_SURF 2
 struct drm_qxl_reloc {
- uint64_t src_offset;
- uint64_t dst_offset;
+  uint64_t src_offset;
+  uint64_t dst_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t src_handle;
- uint32_t dst_handle;
- uint32_t reloc_type;
- uint32_t pad;
+  uint32_t src_handle;
+  uint32_t dst_handle;
+  uint32_t reloc_type;
+  uint32_t pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_qxl_command {
- uint64_t __user command;
- uint64_t __user relocs;
+  uint64_t __user command;
+  uint64_t __user relocs;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t type;
- uint32_t command_size;
- uint32_t relocs_num;
- uint32_t pad;
+  uint32_t type;
+  uint32_t command_size;
+  uint32_t relocs_num;
+  uint32_t pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_qxl_execbuffer {
- uint32_t flags;
- uint32_t commands_num;
+  uint32_t flags;
+  uint32_t commands_num;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t __user commands;
+  uint64_t __user commands;
 };
 struct drm_qxl_update_area {
- uint32_t handle;
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t top;
- uint32_t left;
- uint32_t bottom;
- uint32_t right;
+  uint32_t top;
+  uint32_t left;
+  uint32_t bottom;
+  uint32_t right;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pad;
+  uint32_t pad;
 };
 #define QXL_PARAM_NUM_SURFACES 1
 #define QXL_PARAM_MAX_RELOCS 2
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_qxl_getparam {
- uint64_t param;
- uint64_t value;
+  uint64_t param;
+  uint64_t value;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_qxl_clientcap {
- uint32_t index;
- uint32_t pad;
+  uint32_t index;
+  uint32_t pad;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_qxl_alloc_surf {
- uint32_t format;
- uint32_t width;
- uint32_t height;
+  uint32_t format;
+  uint32_t width;
+  uint32_t height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int32_t stride;
- uint32_t handle;
- uint32_t pad;
+  int32_t stride;
+  uint32_t handle;
+  uint32_t pad;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_QXL_ALLOC   DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
-#define DRM_IOCTL_QXL_MAP   DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
-#define DRM_IOCTL_QXL_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,  struct drm_qxl_execbuffer)
-#define DRM_IOCTL_QXL_UPDATE_AREA   DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,  struct drm_qxl_update_area)
+#define DRM_IOCTL_QXL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
+#define DRM_IOCTL_QXL_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
+#define DRM_IOCTL_QXL_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER, struct drm_qxl_execbuffer)
+#define DRM_IOCTL_QXL_UPDATE_AREA DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA, struct drm_qxl_update_area)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_QXL_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,  struct drm_qxl_getparam)
-#define DRM_IOCTL_QXL_CLIENTCAP   DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,  struct drm_qxl_clientcap)
-#define DRM_IOCTL_QXL_ALLOC_SURF   DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,  struct drm_qxl_alloc_surf)
+#define DRM_IOCTL_QXL_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM, struct drm_qxl_getparam)
+#define DRM_IOCTL_QXL_CLIENTCAP DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP, struct drm_qxl_clientcap)
+#define DRM_IOCTL_QXL_ALLOC_SURF DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF, struct drm_qxl_alloc_surf)
 #endif
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
diff --git a/libc/kernel/uapi/drm/r128_drm.h b/libc/kernel/uapi/drm/r128_drm.h
index 0b2c1c9..4e68381 100644
--- a/libc/kernel/uapi/drm/r128_drm.h
+++ b/libc/kernel/uapi/drm/r128_drm.h
@@ -64,61 +64,61 @@
 #define R128_MAX_TEXTURE_UNITS 2
 #endif
 typedef struct {
- unsigned int dst_pitch_offset_c;
+  unsigned int dst_pitch_offset_c;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int dp_gui_master_cntl_c;
- unsigned int sc_top_left_c;
- unsigned int sc_bottom_right_c;
- unsigned int z_offset_c;
+  unsigned int dp_gui_master_cntl_c;
+  unsigned int sc_top_left_c;
+  unsigned int sc_bottom_right_c;
+  unsigned int z_offset_c;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int z_pitch_c;
- unsigned int z_sten_cntl_c;
- unsigned int tex_cntl_c;
- unsigned int misc_3d_state_cntl_reg;
+  unsigned int z_pitch_c;
+  unsigned int z_sten_cntl_c;
+  unsigned int tex_cntl_c;
+  unsigned int misc_3d_state_cntl_reg;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int texture_clr_cmp_clr_c;
- unsigned int texture_clr_cmp_msk_c;
- unsigned int fog_color_c;
- unsigned int tex_size_pitch_c;
+  unsigned int texture_clr_cmp_clr_c;
+  unsigned int texture_clr_cmp_msk_c;
+  unsigned int fog_color_c;
+  unsigned int tex_size_pitch_c;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int constant_color_c;
- unsigned int pm4_vc_fpu_setup;
- unsigned int setup_cntl;
- unsigned int dp_write_mask;
+  unsigned int constant_color_c;
+  unsigned int pm4_vc_fpu_setup;
+  unsigned int setup_cntl;
+  unsigned int dp_write_mask;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int sten_ref_mask_c;
- unsigned int plane_3d_mask_c;
- unsigned int window_xy_offset;
- unsigned int scale_3d_cntl;
+  unsigned int sten_ref_mask_c;
+  unsigned int plane_3d_mask_c;
+  unsigned int window_xy_offset;
+  unsigned int scale_3d_cntl;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_r128_context_regs_t;
 typedef struct {
- unsigned int tex_cntl;
- unsigned int tex_combine_cntl;
+  unsigned int tex_cntl;
+  unsigned int tex_combine_cntl;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int tex_size_pitch;
- unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
- unsigned int tex_border_color;
+  unsigned int tex_size_pitch;
+  unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
+  unsigned int tex_border_color;
 } drm_r128_texture_regs_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_r128_sarea {
- drm_r128_context_regs_t context_state;
- drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
- unsigned int dirty;
+  drm_r128_context_regs_t context_state;
+  drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
+  unsigned int dirty;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int vertsize;
- unsigned int vc_format;
- struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
- unsigned int nbox;
+  unsigned int vertsize;
+  unsigned int vc_format;
+  struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
+  unsigned int nbox;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int last_frame;
- unsigned int last_dispatch;
- struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
- unsigned int tex_age[R128_NR_TEX_HEAPS];
+  unsigned int last_frame;
+  unsigned int last_dispatch;
+  struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
+  unsigned int tex_age[R128_NR_TEX_HEAPS];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int ctx_owner;
- int pfAllowPageFlip;
- int pfCurrentPage;
+  int ctx_owner;
+  int pfAllowPageFlip;
+  int pfCurrentPage;
 } drm_r128_sarea_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_R128_INIT 0x00
@@ -143,138 +143,138 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_R128_GETPARAM 0x12
 #define DRM_R128_FLIP 0x13
-#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
-#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START)
+#define DRM_IOCTL_R128_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
+#define DRM_IOCTL_R128_CCE_START DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_START)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
-#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
-#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
-#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET)
+#define DRM_IOCTL_R128_CCE_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
+#define DRM_IOCTL_R128_CCE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
+#define DRM_IOCTL_R128_CCE_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
+#define DRM_IOCTL_R128_RESET DRM_IO(DRM_COMMAND_BASE + DRM_R128_RESET)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP)
-#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
-#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
-#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
+#define DRM_IOCTL_R128_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_R128_SWAP)
+#define DRM_IOCTL_R128_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
+#define DRM_IOCTL_R128_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
+#define DRM_IOCTL_R128_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
-#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
-#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
+#define DRM_IOCTL_R128_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
+#define DRM_IOCTL_R128_DEPTH DRM_IOW(DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
+#define DRM_IOCTL_R128_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
 #define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
-#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
-#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
-#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP)
+#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
+#define DRM_IOCTL_R128_CLEAR2 DRM_IOW(DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
+#define DRM_IOCTL_R128_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
+#define DRM_IOCTL_R128_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_R128_FLIP)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_r128_init {
- enum {
- R128_INIT_CCE = 0x01,
- R128_CLEANUP_CCE = 0x02
+  enum {
+    R128_INIT_CCE = 0x01,
+    R128_CLEANUP_CCE = 0x02
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } func;
- unsigned long sarea_priv_offset;
- int is_pci;
- int cce_mode;
+  } func;
+  unsigned long sarea_priv_offset;
+  int is_pci;
+  int cce_mode;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int cce_secure;
- int ring_size;
- int usec_timeout;
- unsigned int fb_bpp;
+  int cce_secure;
+  int ring_size;
+  int usec_timeout;
+  unsigned int fb_bpp;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int front_offset, front_pitch;
- unsigned int back_offset, back_pitch;
- unsigned int depth_bpp;
- unsigned int depth_offset, depth_pitch;
+  unsigned int front_offset, front_pitch;
+  unsigned int back_offset, back_pitch;
+  unsigned int depth_bpp;
+  unsigned int depth_offset, depth_pitch;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int span_offset;
- unsigned long fb_offset;
- unsigned long mmio_offset;
- unsigned long ring_offset;
+  unsigned int span_offset;
+  unsigned long fb_offset;
+  unsigned long mmio_offset;
+  unsigned long ring_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long ring_rptr_offset;
- unsigned long buffers_offset;
- unsigned long agp_textures_offset;
+  unsigned long ring_rptr_offset;
+  unsigned long buffers_offset;
+  unsigned long agp_textures_offset;
 } drm_r128_init_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_r128_cce_stop {
- int flush;
- int idle;
+  int flush;
+  int idle;
 } drm_r128_cce_stop_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_r128_clear {
- unsigned int flags;
- unsigned int clear_color;
- unsigned int clear_depth;
+  unsigned int flags;
+  unsigned int clear_color;
+  unsigned int clear_depth;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int color_mask;
- unsigned int depth_mask;
+  unsigned int color_mask;
+  unsigned int depth_mask;
 } drm_r128_clear_t;
 typedef struct drm_r128_vertex {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int prim;
- int idx;
- int count;
- int discard;
+  int prim;
+  int idx;
+  int count;
+  int discard;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_r128_vertex_t;
 typedef struct drm_r128_indices {
- int prim;
- int idx;
+  int prim;
+  int idx;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int start;
- int end;
- int discard;
+  int start;
+  int end;
+  int discard;
 } drm_r128_indices_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_r128_blit {
- int idx;
- int pitch;
- int offset;
+  int idx;
+  int pitch;
+  int offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int format;
- unsigned short x, y;
- unsigned short width, height;
+  int format;
+  unsigned short x, y;
+  unsigned short width, height;
 } drm_r128_blit_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_r128_depth {
- enum {
- R128_WRITE_SPAN = 0x01,
- R128_WRITE_PIXELS = 0x02,
+  enum {
+    R128_WRITE_SPAN = 0x01,
+    R128_WRITE_PIXELS = 0x02,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- R128_READ_SPAN = 0x03,
- R128_READ_PIXELS = 0x04
- } func;
- int n;
+    R128_READ_SPAN = 0x03,
+    R128_READ_PIXELS = 0x04
+  } func;
+  int n;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int __user *x;
- int __user *y;
- unsigned int __user *buffer;
- unsigned char __user *mask;
+  int __user * x;
+  int __user * y;
+  unsigned int __user * buffer;
+  unsigned char __user * mask;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_r128_depth_t;
 typedef struct drm_r128_stipple {
- unsigned int __user *mask;
+  unsigned int __user * mask;
 } drm_r128_stipple_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_r128_indirect {
- int idx;
- int start;
- int end;
+  int idx;
+  int start;
+  int end;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int discard;
+  int discard;
 } drm_r128_indirect_t;
 typedef struct drm_r128_fullscreen {
- enum {
+  enum {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- R128_INIT_FULLSCREEN = 0x01,
- R128_CLEANUP_FULLSCREEN = 0x02
- } func;
+    R128_INIT_FULLSCREEN = 0x01,
+    R128_CLEANUP_FULLSCREEN = 0x02
+  } func;
 } drm_r128_fullscreen_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define R128_PARAM_IRQ_NR 1
 typedef struct drm_r128_getparam {
- int param;
- void __user *value;
+  int param;
+  void __user * value;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_r128_getparam_t;
 #endif
diff --git a/libc/kernel/uapi/drm/radeon_drm.h b/libc/kernel/uapi/drm/radeon_drm.h
index d5c1138..6fb86f1 100644
--- a/libc/kernel/uapi/drm/radeon_drm.h
+++ b/libc/kernel/uapi/drm/radeon_drm.h
@@ -179,34 +179,34 @@
 #define RADEON_CMD_WAIT 8
 #define RADEON_CMD_VECLINEAR 9
 typedef union {
- int i;
+  int i;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct {
- unsigned char cmd_type, pad0, pad1, pad2;
- } header;
- struct {
+  struct {
+    unsigned char cmd_type, pad0, pad1, pad2;
+  } header;
+  struct {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned char cmd_type, packet_id, pad0, pad1;
- } packet;
- struct {
- unsigned char cmd_type, offset, stride, count;
+    unsigned char cmd_type, packet_id, pad0, pad1;
+  } packet;
+  struct {
+    unsigned char cmd_type, offset, stride, count;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } scalars;
- struct {
- unsigned char cmd_type, offset, stride, count;
- } vectors;
+  } scalars;
+  struct {
+    unsigned char cmd_type, offset, stride, count;
+  } vectors;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct {
- unsigned char cmd_type, addr_lo, addr_hi, count;
- } veclinear;
- struct {
+  struct {
+    unsigned char cmd_type, addr_lo, addr_hi, count;
+  } veclinear;
+  struct {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned char cmd_type, buf_idx, pad0, pad1;
- } dma;
- struct {
- unsigned char cmd_type, flags, pad0, pad1;
+    unsigned char cmd_type, buf_idx, pad0, pad1;
+  } dma;
+  struct {
+    unsigned char cmd_type, flags, pad0, pad1;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } wait;
+  } wait;
 } drm_radeon_cmd_header_t;
 #define RADEON_WAIT_2D 0x1
 #define RADEON_WAIT_3D 0x2
@@ -236,42 +236,42 @@
 #define R300_CMD_R500FP 9
 typedef union {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int u;
- struct {
- unsigned char cmd_type, pad0, pad1, pad2;
- } header;
+  unsigned int u;
+  struct {
+    unsigned char cmd_type, pad0, pad1, pad2;
+  } header;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct {
- unsigned char cmd_type, count, reglo, reghi;
- } packet0;
- struct {
+  struct {
+    unsigned char cmd_type, count, reglo, reghi;
+  } packet0;
+  struct {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned char cmd_type, count, adrlo, adrhi;
- } vpu;
- struct {
- unsigned char cmd_type, packet, pad0, pad1;
+    unsigned char cmd_type, count, adrlo, adrhi;
+  } vpu;
+  struct {
+    unsigned char cmd_type, packet, pad0, pad1;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } packet3;
- struct {
- unsigned char cmd_type, packet;
- unsigned short count;
+  } packet3;
+  struct {
+    unsigned char cmd_type, packet;
+    unsigned short count;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } delay;
- struct {
- unsigned char cmd_type, buf_idx, pad0, pad1;
- } dma;
+  } delay;
+  struct {
+    unsigned char cmd_type, buf_idx, pad0, pad1;
+  } dma;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct {
- unsigned char cmd_type, flags, pad0, pad1;
- } wait;
- struct {
+  struct {
+    unsigned char cmd_type, flags, pad0, pad1;
+  } wait;
+  struct {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned char cmd_type, reg, n_bufs, flags;
- } scratch;
- struct {
- unsigned char cmd_type, count, adrlo, adrhi_flags;
+    unsigned char cmd_type, reg, n_bufs, flags;
+  } scratch;
+  struct {
+    unsigned char cmd_type, count, adrlo, adrhi_flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } r500fp;
+  } r500fp;
 } drm_r300_cmd_header_t;
 #define RADEON_FRONT 0x1
 #define RADEON_BACK 0x2
@@ -314,677 +314,676 @@
 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
 #endif
 typedef struct {
- unsigned int red;
+  unsigned int red;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int green;
- unsigned int blue;
- unsigned int alpha;
+  unsigned int green;
+  unsigned int blue;
+  unsigned int alpha;
 } radeon_color_regs_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct {
- unsigned int pp_misc;
- unsigned int pp_fog_color;
- unsigned int re_solid_color;
+  unsigned int pp_misc;
+  unsigned int pp_fog_color;
+  unsigned int re_solid_color;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int rb3d_blendcntl;
- unsigned int rb3d_depthoffset;
- unsigned int rb3d_depthpitch;
- unsigned int rb3d_zstencilcntl;
+  unsigned int rb3d_blendcntl;
+  unsigned int rb3d_depthoffset;
+  unsigned int rb3d_depthpitch;
+  unsigned int rb3d_zstencilcntl;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int pp_cntl;
- unsigned int rb3d_cntl;
- unsigned int rb3d_coloroffset;
- unsigned int re_width_height;
+  unsigned int pp_cntl;
+  unsigned int rb3d_cntl;
+  unsigned int rb3d_coloroffset;
+  unsigned int re_width_height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int rb3d_colorpitch;
- unsigned int se_cntl;
- unsigned int se_coord_fmt;
- unsigned int re_line_pattern;
+  unsigned int rb3d_colorpitch;
+  unsigned int se_cntl;
+  unsigned int se_coord_fmt;
+  unsigned int re_line_pattern;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int re_line_state;
- unsigned int se_line_width;
- unsigned int pp_lum_matrix;
- unsigned int pp_rot_matrix_0;
+  unsigned int re_line_state;
+  unsigned int se_line_width;
+  unsigned int pp_lum_matrix;
+  unsigned int pp_rot_matrix_0;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int pp_rot_matrix_1;
- unsigned int rb3d_stencilrefmask;
- unsigned int rb3d_ropcntl;
- unsigned int rb3d_planemask;
+  unsigned int pp_rot_matrix_1;
+  unsigned int rb3d_stencilrefmask;
+  unsigned int rb3d_ropcntl;
+  unsigned int rb3d_planemask;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int se_vport_xscale;
- unsigned int se_vport_xoffset;
- unsigned int se_vport_yscale;
- unsigned int se_vport_yoffset;
+  unsigned int se_vport_xscale;
+  unsigned int se_vport_xoffset;
+  unsigned int se_vport_yscale;
+  unsigned int se_vport_yoffset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int se_vport_zscale;
- unsigned int se_vport_zoffset;
- unsigned int se_cntl_status;
- unsigned int re_top_left;
+  unsigned int se_vport_zscale;
+  unsigned int se_vport_zoffset;
+  unsigned int se_cntl_status;
+  unsigned int re_top_left;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int re_misc;
+  unsigned int re_misc;
 } drm_radeon_context_regs_t;
 typedef struct {
- unsigned int se_zbias_factor;
+  unsigned int se_zbias_factor;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int se_zbias_constant;
+  unsigned int se_zbias_constant;
 } drm_radeon_context2_regs_t;
 typedef struct {
- unsigned int pp_txfilter;
+  unsigned int pp_txfilter;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int pp_txformat;
- unsigned int pp_txoffset;
- unsigned int pp_txcblend;
- unsigned int pp_txablend;
+  unsigned int pp_txformat;
+  unsigned int pp_txoffset;
+  unsigned int pp_txcblend;
+  unsigned int pp_txablend;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int pp_tfactor;
- unsigned int pp_border_color;
+  unsigned int pp_tfactor;
+  unsigned int pp_border_color;
 } drm_radeon_texture_regs_t;
 typedef struct {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int start;
- unsigned int finish;
- unsigned int prim:8;
- unsigned int stateidx:8;
+  unsigned int start;
+  unsigned int finish;
+  unsigned int prim : 8;
+  unsigned int stateidx : 8;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int numverts:16;
- unsigned int vc_format;
+  unsigned int numverts : 16;
+  unsigned int vc_format;
 } drm_radeon_prim_t;
 typedef struct {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_radeon_context_regs_t context;
- drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
- drm_radeon_context2_regs_t context2;
- unsigned int dirty;
+  drm_radeon_context_regs_t context;
+  drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
+  drm_radeon_context2_regs_t context2;
+  unsigned int dirty;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_radeon_state_t;
 typedef struct {
- drm_radeon_context_regs_t context_state;
- drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
+  drm_radeon_context_regs_t context_state;
+  drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int dirty;
- unsigned int vertsize;
- unsigned int vc_format;
- struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
+  unsigned int dirty;
+  unsigned int vertsize;
+  unsigned int vc_format;
+  struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int nbox;
- unsigned int last_frame;
- unsigned int last_dispatch;
- unsigned int last_clear;
+  unsigned int nbox;
+  unsigned int last_frame;
+  unsigned int last_dispatch;
+  unsigned int last_clear;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
- 1];
- unsigned int tex_age[RADEON_NR_TEX_HEAPS];
- int ctx_owner;
+  struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1];
+  unsigned int tex_age[RADEON_NR_TEX_HEAPS];
+  int ctx_owner;
+  int pfState;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int pfState;
- int pfCurrentPage;
- int crtc2_base;
- int tiling_enabled;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  int pfCurrentPage;
+  int crtc2_base;
+  int tiling_enabled;
 } drm_radeon_sarea_t;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_CP_INIT 0x00
 #define DRM_RADEON_CP_START 0x01
 #define DRM_RADEON_CP_STOP 0x02
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_CP_RESET 0x03
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_CP_IDLE 0x04
 #define DRM_RADEON_RESET 0x05
 #define DRM_RADEON_FULLSCREEN 0x06
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_SWAP 0x07
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_CLEAR 0x08
 #define DRM_RADEON_VERTEX 0x09
 #define DRM_RADEON_INDICES 0x0A
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_NOT_USED
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_STIPPLE 0x0C
 #define DRM_RADEON_INDIRECT 0x0D
 #define DRM_RADEON_TEXTURE 0x0E
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_VERTEX2 0x0F
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_CMDBUF 0x10
 #define DRM_RADEON_GETPARAM 0x11
 #define DRM_RADEON_FLIP 0x12
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_ALLOC 0x13
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_FREE 0x14
 #define DRM_RADEON_INIT_HEAP 0x15
 #define DRM_RADEON_IRQ_EMIT 0x16
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_IRQ_WAIT 0x17
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_CP_RESUME 0x18
 #define DRM_RADEON_SETPARAM 0x19
 #define DRM_RADEON_SURF_ALLOC 0x1a
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_SURF_FREE 0x1b
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_GEM_INFO 0x1c
 #define DRM_RADEON_GEM_CREATE 0x1d
 #define DRM_RADEON_GEM_MMAP 0x1e
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_GEM_PREAD 0x21
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_GEM_PWRITE 0x22
 #define DRM_RADEON_GEM_SET_DOMAIN 0x23
 #define DRM_RADEON_GEM_WAIT_IDLE 0x24
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_CS 0x26
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_INFO 0x27
 #define DRM_RADEON_GEM_SET_TILING 0x28
 #define DRM_RADEON_GEM_GET_TILING 0x29
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_GEM_BUSY 0x2a
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_GEM_VA 0x2b
 #define DRM_RADEON_GEM_OP 0x2c
 #define DRM_RADEON_GEM_USERPTR 0x2d
+#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
-#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
-#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
-#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
+#define DRM_IOCTL_RADEON_CP_START DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START)
+#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
+#define DRM_IOCTL_RADEON_CP_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
+#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
-#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
-#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
-#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
+#define DRM_IOCTL_RADEON_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET)
+#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
+#define DRM_IOCTL_RADEON_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP)
+#define DRM_IOCTL_RADEON_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
-#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
-#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
-#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define DRM_IOCTL_RADEON_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
+#define DRM_IOCTL_RADEON_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
+#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
-#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
-#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
+#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
-#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define DRM_IOCTL_RADEON_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP)
 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
-#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
+#define DRM_IOCTL_RADEON_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
+#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
-#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
-#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
+#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
+#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
+#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
-#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
-#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
+#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
+#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
 #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
 #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
 #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
 #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
 #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
 #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
 typedef struct drm_radeon_init {
- enum {
+  enum {
+    RADEON_INIT_CP = 0x01,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- RADEON_INIT_CP = 0x01,
- RADEON_CLEANUP_CP = 0x02,
- RADEON_INIT_R200_CP = 0x03,
- RADEON_INIT_R300_CP = 0x04,
+    RADEON_CLEANUP_CP = 0x02,
+    RADEON_INIT_R200_CP = 0x03,
+    RADEON_INIT_R300_CP = 0x04,
+    RADEON_INIT_R600_CP = 0x05
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- RADEON_INIT_R600_CP = 0x05
- } func;
- unsigned long sarea_priv_offset;
- int is_pci;
+  } func;
+  unsigned long sarea_priv_offset;
+  int is_pci;
+  int cp_mode;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int cp_mode;
- int gart_size;
- int ring_size;
- int usec_timeout;
+  int gart_size;
+  int ring_size;
+  int usec_timeout;
+  unsigned int fb_bpp;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int fb_bpp;
- unsigned int front_offset, front_pitch;
- unsigned int back_offset, back_pitch;
- unsigned int depth_bpp;
+  unsigned int front_offset, front_pitch;
+  unsigned int back_offset, back_pitch;
+  unsigned int depth_bpp;
+  unsigned int depth_offset, depth_pitch;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int depth_offset, depth_pitch;
- unsigned long fb_offset;
- unsigned long mmio_offset;
- unsigned long ring_offset;
+  unsigned long fb_offset;
+  unsigned long mmio_offset;
+  unsigned long ring_offset;
+  unsigned long ring_rptr_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long ring_rptr_offset;
- unsigned long buffers_offset;
- unsigned long gart_textures_offset;
+  unsigned long buffers_offset;
+  unsigned long gart_textures_offset;
 } drm_radeon_init_t;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_radeon_cp_stop {
- int flush;
- int idle;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  int flush;
+  int idle;
 } drm_radeon_cp_stop_t;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_radeon_fullscreen {
- enum {
- RADEON_INIT_FULLSCREEN = 0x01,
- RADEON_CLEANUP_FULLSCREEN = 0x02
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } func;
+  enum {
+    RADEON_INIT_FULLSCREEN = 0x01,
+    RADEON_CLEANUP_FULLSCREEN = 0x02
+  } func;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_radeon_fullscreen_t;
 #define CLEAR_X1 0
 #define CLEAR_Y1 1
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define CLEAR_X2 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define CLEAR_Y2 3
 #define CLEAR_DEPTH 4
 typedef union drm_radeon_clear_rect {
+  float f[5];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- float f[5];
- unsigned int ui[5];
+  unsigned int ui[5];
 } drm_radeon_clear_rect_t;
 typedef struct drm_radeon_clear {
+  unsigned int flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int flags;
- unsigned int clear_color;
- unsigned int clear_depth;
- unsigned int color_mask;
+  unsigned int clear_color;
+  unsigned int clear_depth;
+  unsigned int color_mask;
+  unsigned int depth_mask;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int depth_mask;
- drm_radeon_clear_rect_t __user *depth_boxes;
+  drm_radeon_clear_rect_t __user * depth_boxes;
 } drm_radeon_clear_t;
 typedef struct drm_radeon_vertex {
+  int prim;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int prim;
- int idx;
- int count;
- int discard;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  int idx;
+  int count;
+  int discard;
 } drm_radeon_vertex_t;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_radeon_indices {
- int prim;
- int idx;
+  int prim;
+  int idx;
+  int start;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int start;
- int end;
- int discard;
+  int end;
+  int discard;
 } drm_radeon_indices_t;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_radeon_vertex2 {
- int idx;
- int discard;
- int nr_states;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_radeon_state_t __user *state;
- int nr_prims;
- drm_radeon_prim_t __user *prim;
+  int idx;
+  int discard;
+  int nr_states;
+  drm_radeon_state_t __user * state;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  int nr_prims;
+  drm_radeon_prim_t __user * prim;
 } drm_radeon_vertex2_t;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_radeon_cmd_buffer {
- int bufsz;
- char __user *buf;
- int nbox;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_clip_rect __user *boxes;
+  int bufsz;
+  char __user * buf;
+  int nbox;
+  struct drm_clip_rect __user * boxes;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_radeon_cmd_buffer_t;
 typedef struct drm_radeon_tex_image {
- unsigned int x, y;
+  unsigned int x, y;
+  unsigned int width, height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int width, height;
- const void __user *data;
+  const void __user * data;
 } drm_radeon_tex_image_t;
 typedef struct drm_radeon_texture {
+  unsigned int offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int offset;
- int pitch;
- int format;
- int width;
+  int pitch;
+  int format;
+  int width;
+  int height;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int height;
- drm_radeon_tex_image_t __user *image;
+  drm_radeon_tex_image_t __user * image;
 } drm_radeon_texture_t;
 typedef struct drm_radeon_stipple {
+  unsigned int __user * mask;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int __user *mask;
 } drm_radeon_stipple_t;
 typedef struct drm_radeon_indirect {
- int idx;
+  int idx;
+  int start;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int start;
- int end;
- int discard;
+  int end;
+  int discard;
 } drm_radeon_indirect_t;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_CARD_PCI 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_CARD_AGP 1
 #define RADEON_CARD_PCIE 2
 #define RADEON_PARAM_GART_BUFFER_OFFSET 1
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_PARAM_LAST_FRAME 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_PARAM_LAST_DISPATCH 3
 #define RADEON_PARAM_LAST_CLEAR 4
 #define RADEON_PARAM_IRQ_NR 5
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_PARAM_GART_BASE 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_PARAM_REGISTER_HANDLE 7
 #define RADEON_PARAM_STATUS_HANDLE 8
 #define RADEON_PARAM_SAREA_HANDLE 9
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_PARAM_GART_TEX_HANDLE 10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_PARAM_SCRATCH_OFFSET 11
 #define RADEON_PARAM_CARD_TYPE 12
 #define RADEON_PARAM_VBLANK_CRTC 13
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_PARAM_FB_LOCATION 14
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_PARAM_NUM_GB_PIPES 15
 #define RADEON_PARAM_DEVICE_ID 16
 #define RADEON_PARAM_NUM_Z_PIPES 17
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_radeon_getparam {
- int param;
- void __user *value;
-} drm_radeon_getparam_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  int param;
+  void __user * value;
+} drm_radeon_getparam_t;
 #define RADEON_MEM_REGION_GART 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_MEM_REGION_FB 2
 typedef struct drm_radeon_mem_alloc {
- int region;
+  int region;
+  int alignment;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int alignment;
- int size;
- int __user *region_offset;
+  int size;
+  int __user * region_offset;
 } drm_radeon_mem_alloc_t;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_radeon_mem_free {
- int region;
- int region_offset;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  int region;
+  int region_offset;
 } drm_radeon_mem_free_t;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_radeon_mem_init_heap {
- int region;
- int size;
- int start;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  int region;
+  int size;
+  int start;
 } drm_radeon_mem_init_heap_t;
-typedef struct drm_radeon_irq_emit {
- int __user *irq_seq;
-} drm_radeon_irq_emit_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+typedef struct drm_radeon_irq_emit {
+  int __user * irq_seq;
+} drm_radeon_irq_emit_t;
 typedef struct drm_radeon_irq_wait {
- int irq_seq;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  int irq_seq;
 } drm_radeon_irq_wait_t;
 typedef struct drm_radeon_setparam {
+  unsigned int param;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int param;
- __s64 value;
+  __s64 value;
 } drm_radeon_setparam_t;
 #define RADEON_SETPARAM_FB_LOCATION 1
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_SETPARAM_SWITCH_TILING 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_SETPARAM_PCIGART_LOCATION 3
 #define RADEON_SETPARAM_NEW_MEMMAP 4
 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_SETPARAM_VBLANK_CRTC 6
-typedef struct drm_radeon_surface_alloc {
- unsigned int address;
- unsigned int size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int flags;
+typedef struct drm_radeon_surface_alloc {
+  unsigned int address;
+  unsigned int size;
+  unsigned int flags;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_radeon_surface_alloc_t;
 typedef struct drm_radeon_surface_free {
- unsigned int address;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  unsigned int address;
 } drm_radeon_surface_free_t;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_RADEON_VBLANK_CRTC1 1
 #define DRM_RADEON_VBLANK_CRTC2 2
 #define RADEON_GEM_DOMAIN_CPU 0x1
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_GEM_DOMAIN_GTT 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_GEM_DOMAIN_VRAM 0x4
 struct drm_radeon_gem_info {
- uint64_t gart_size;
+  uint64_t gart_size;
+  uint64_t vram_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t vram_size;
- uint64_t vram_visible;
+  uint64_t vram_visible;
 };
 #define RADEON_GEM_NO_BACKING_STORE (1 << 0)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_GEM_GTT_UC (1 << 1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_GEM_GTT_WC (1 << 2)
 #define RADEON_GEM_CPU_ACCESS (1 << 3)
 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_radeon_gem_create {
- uint64_t size;
- uint64_t alignment;
- uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t initial_domain;
- uint32_t flags;
+  uint64_t size;
+  uint64_t alignment;
+  uint32_t handle;
+  uint32_t initial_domain;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  uint32_t flags;
 };
 #define RADEON_GEM_USERPTR_READONLY (1 << 0)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
 #define RADEON_GEM_USERPTR_REGISTER (1 << 3)
 struct drm_radeon_gem_userptr {
+  uint64_t addr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t addr;
- uint64_t size;
- uint32_t flags;
- uint32_t handle;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  uint64_t size;
+  uint32_t flags;
+  uint32_t handle;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_TILING_MACRO 0x1
 #define RADEON_TILING_MICRO 0x2
 #define RADEON_TILING_SWAP_16BIT 0x4
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_TILING_SWAP_32BIT 0x8
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_TILING_SURFACE 0x10
 #define RADEON_TILING_MICRO_SQUARE 0x20
 #define RADEON_TILING_EG_BANKW_SHIFT 8
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_TILING_EG_BANKW_MASK 0xf
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_TILING_EG_BANKH_SHIFT 12
 #define RADEON_TILING_EG_BANKH_MASK 0xf
 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
 #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
-struct drm_radeon_gem_set_tiling {
- uint32_t handle;
- uint32_t tiling_flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pitch;
+struct drm_radeon_gem_set_tiling {
+  uint32_t handle;
+  uint32_t tiling_flags;
+  uint32_t pitch;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_radeon_gem_get_tiling {
- uint32_t handle;
+  uint32_t handle;
+  uint32_t tiling_flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t tiling_flags;
- uint32_t pitch;
+  uint32_t pitch;
 };
 struct drm_radeon_gem_mmap {
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t pad;
- uint64_t offset;
- uint64_t size;
+  uint32_t pad;
+  uint64_t offset;
+  uint64_t size;
+  uint64_t addr_ptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t addr_ptr;
 };
 struct drm_radeon_gem_set_domain {
- uint32_t handle;
+  uint32_t handle;
+  uint32_t read_domains;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t read_domains;
- uint32_t write_domain;
+  uint32_t write_domain;
 };
 struct drm_radeon_gem_wait_idle {
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t pad;
+  uint32_t pad;
 };
 struct drm_radeon_gem_busy {
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t domain;
+  uint32_t domain;
 };
 struct drm_radeon_gem_pread {
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t pad;
- uint64_t offset;
- uint64_t size;
+  uint32_t pad;
+  uint64_t offset;
+  uint64_t size;
+  uint64_t data_ptr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t data_ptr;
 };
 struct drm_radeon_gem_pwrite {
- uint32_t handle;
+  uint32_t handle;
+  uint32_t pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pad;
- uint64_t offset;
- uint64_t size;
- uint64_t data_ptr;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  uint64_t offset;
+  uint64_t size;
+  uint64_t data_ptr;
 };
-struct drm_radeon_gem_op {
- uint32_t handle;
- uint32_t op;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t value;
+struct drm_radeon_gem_op {
+  uint32_t handle;
+  uint32_t op;
+  uint64_t value;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
 #define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_VA_MAP 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_VA_UNMAP 2
 #define RADEON_VA_RESULT_OK 0
 #define RADEON_VA_RESULT_ERROR 1
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_VA_RESULT_VA_EXIST 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_VM_PAGE_VALID (1 << 0)
 #define RADEON_VM_PAGE_READABLE (1 << 1)
 #define RADEON_VM_PAGE_WRITEABLE (1 << 2)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_VM_PAGE_SYSTEM (1 << 3)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_VM_PAGE_SNOOPED (1 << 4)
 struct drm_radeon_gem_va {
- uint32_t handle;
+  uint32_t handle;
+  uint32_t operation;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t operation;
- uint32_t vm_id;
- uint32_t flags;
- uint64_t offset;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  uint32_t vm_id;
+  uint32_t flags;
+  uint64_t offset;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_CHUNK_ID_RELOCS 0x01
 #define RADEON_CHUNK_ID_IB 0x02
 #define RADEON_CHUNK_ID_FLAGS 0x03
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_CHUNK_ID_CONST_IB 0x04
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
 #define RADEON_CS_USE_VM 0x02
 #define RADEON_CS_END_OF_FRAME 0x04
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_CS_RING_GFX 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_CS_RING_COMPUTE 1
 #define RADEON_CS_RING_DMA 2
 #define RADEON_CS_RING_UVD 3
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_CS_RING_VCE 4
-struct drm_radeon_cs_chunk {
- uint32_t chunk_id;
- uint32_t length_dw;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t chunk_data;
+struct drm_radeon_cs_chunk {
+  uint32_t chunk_id;
+  uint32_t length_dw;
+  uint64_t chunk_data;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define RADEON_RELOC_PRIO_MASK (0xf << 0)
 struct drm_radeon_cs_reloc {
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t read_domains;
- uint32_t write_domain;
- uint32_t flags;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  uint32_t read_domains;
+  uint32_t write_domain;
+  uint32_t flags;
 };
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_radeon_cs {
- uint32_t num_chunks;
- uint32_t cs_id;
+  uint32_t num_chunks;
+  uint32_t cs_id;
+  uint64_t chunks;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t chunks;
- uint64_t gart_limit;
- uint64_t vram_limit;
+  uint64_t gart_limit;
+  uint64_t vram_limit;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_DEVICE_ID 0x00
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_NUM_GB_PIPES 0x01
 #define RADEON_INFO_NUM_Z_PIPES 0x02
 #define RADEON_INFO_ACCEL_WORKING 0x03
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_CRTC_FROM_ID 0x04
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_ACCEL_WORKING2 0x05
 #define RADEON_INFO_TILING_CONFIG 0x06
 #define RADEON_INFO_WANT_HYPERZ 0x07
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_WANT_CMASK 0x08
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09
 #define RADEON_INFO_NUM_BACKENDS 0x0a
 #define RADEON_INFO_NUM_TILE_PIPES 0x0b
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_FUSION_GART_WORKING 0x0c
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_BACKEND_MAP 0x0d
 #define RADEON_INFO_VA_START 0x0e
 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_MAX_PIPES 0x10
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_TIMESTAMP 0x11
 #define RADEON_INFO_MAX_SE 0x12
 #define RADEON_INFO_MAX_SH_PER_SE 0x13
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_FASTFB_WORKING 0x14
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_RING_WORKING 0x15
 #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
 #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
 #define RADEON_INFO_MAX_SCLK 0x1a
 #define RADEON_INFO_VCE_FW_VERSION 0x1b
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_VCE_FB_VERSION 0x1c
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_NUM_BYTES_MOVED 0x1d
 #define RADEON_INFO_VRAM_USAGE 0x1e
 #define RADEON_INFO_GTT_USAGE 0x1f
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
-struct drm_radeon_info {
- uint32_t request;
- uint32_t pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t value;
+struct drm_radeon_info {
+  uint32_t request;
+  uint32_t pad;
+  uint64_t value;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
 #define SI_TILE_MODE_COLOR_1D 13
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SI_TILE_MODE_COLOR_1D_SCANOUT 9
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SI_TILE_MODE_COLOR_2D_8BPP 14
 #define SI_TILE_MODE_COLOR_2D_16BPP 15
 #define SI_TILE_MODE_COLOR_2D_32BPP 16
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SI_TILE_MODE_COLOR_2D_64BPP 17
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
 #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
 #define SI_TILE_MODE_DEPTH_STENCIL_1D 4
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SI_TILE_MODE_DEPTH_STENCIL_2D 0
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
diff --git a/libc/kernel/uapi/drm/savage_drm.h b/libc/kernel/uapi/drm/savage_drm.h
index 4c1d0f8..db873b6 100644
--- a/libc/kernel/uapi/drm/savage_drm.h
+++ b/libc/kernel/uapi/drm/savage_drm.h
@@ -29,156 +29,155 @@
 #define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
 #endif
 typedef struct _drm_savage_sarea {
- struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS +
+  struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + 1];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- 1];
- unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
- int ctxOwner;
-} drm_savage_sarea_t, *drm_savage_sarea_ptr;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
+  int ctxOwner;
+} drm_savage_sarea_t, * drm_savage_sarea_ptr;
 #define DRM_SAVAGE_BCI_INIT 0x00
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_SAVAGE_BCI_CMDBUF 0x01
 #define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
 #define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
+#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
-#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
+#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
 #define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
-#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
 #define SAVAGE_DMA_PCI 1
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_DMA_AGP 3
 typedef struct drm_savage_init {
- enum {
+  enum {
+    SAVAGE_INIT_BCI = 1,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- SAVAGE_INIT_BCI = 1,
- SAVAGE_CLEANUP_BCI = 2
- } func;
- unsigned int sarea_priv_offset;
+    SAVAGE_CLEANUP_BCI = 2
+  } func;
+  unsigned int sarea_priv_offset;
+  unsigned int cob_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int cob_size;
- unsigned int bci_threshold_lo, bci_threshold_hi;
- unsigned int dma_type;
- unsigned int fb_bpp;
+  unsigned int bci_threshold_lo, bci_threshold_hi;
+  unsigned int dma_type;
+  unsigned int fb_bpp;
+  unsigned int front_offset, front_pitch;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int front_offset, front_pitch;
- unsigned int back_offset, back_pitch;
- unsigned int depth_bpp;
- unsigned int depth_offset, depth_pitch;
+  unsigned int back_offset, back_pitch;
+  unsigned int depth_bpp;
+  unsigned int depth_offset, depth_pitch;
+  unsigned int texture_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int texture_offset;
- unsigned int texture_size;
- unsigned long status_offset;
- unsigned long buffers_offset;
+  unsigned int texture_size;
+  unsigned long status_offset;
+  unsigned long buffers_offset;
+  unsigned long agp_textures_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long agp_textures_offset;
- unsigned long cmd_dma_offset;
+  unsigned long cmd_dma_offset;
 } drm_savage_init_t;
 typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct drm_savage_cmdbuf {
- drm_savage_cmd_header_t __user *cmd_addr;
- unsigned int size;
- unsigned int dma_idx;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int discard;
- unsigned int __user *vb_addr;
- unsigned int vb_size;
- unsigned int vb_stride;
+  drm_savage_cmd_header_t __user * cmd_addr;
+  unsigned int size;
+  unsigned int dma_idx;
+  int discard;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_clip_rect __user *box_addr;
- unsigned int nbox;
+  unsigned int __user * vb_addr;
+  unsigned int vb_size;
+  unsigned int vb_stride;
+  struct drm_clip_rect __user * box_addr;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+  unsigned int nbox;
 } drm_savage_cmdbuf_t;
 #define SAVAGE_WAIT_2D 0x1
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_WAIT_3D 0x2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_WAIT_IRQ 0x4
 typedef struct drm_savage_event {
- unsigned int count;
+  unsigned int count;
+  unsigned int flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int flags;
 } drm_savage_event_emit_t, drm_savage_event_wait_t;
 #define SAVAGE_CMD_STATE 0
 #define SAVAGE_CMD_DMA_PRIM 1
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_CMD_VB_PRIM 2
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_CMD_DMA_IDX 3
 #define SAVAGE_CMD_VB_IDX 4
 #define SAVAGE_CMD_CLEAR 5
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_CMD_SWAP 6
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_PRIM_TRILIST 0
 #define SAVAGE_PRIM_TRISTRIP 1
 #define SAVAGE_PRIM_TRIFAN 2
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_PRIM_TRILIST_201 3
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_SKIP_Z 0x01
 #define SAVAGE_SKIP_W 0x02
 #define SAVAGE_SKIP_C0 0x04
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_SKIP_C1 0x08
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_SKIP_S0 0x10
 #define SAVAGE_SKIP_T0 0x20
 #define SAVAGE_SKIP_ST0 0x30
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_SKIP_S1 0x40
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_SKIP_T1 0x80
 #define SAVAGE_SKIP_ST1 0xc0
 #define SAVAGE_SKIP_ALL_S3D 0x3f
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_SKIP_ALL_S4 0xff
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define SAVAGE_FRONT 0x1
 #define SAVAGE_BACK 0x2
 #define SAVAGE_DEPTH 0x4
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 union drm_savage_cmd_header {
- struct {
- unsigned char cmd;
- unsigned char pad0;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned short pad1;
- unsigned short pad2;
- unsigned short pad3;
- } cmd;
+  struct {
+    unsigned char cmd;
+    unsigned char pad0;
+    unsigned short pad1;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct {
- unsigned char cmd;
- unsigned char global;
- unsigned short count;
+    unsigned short pad2;
+    unsigned short pad3;
+  } cmd;
+  struct {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned short start;
- unsigned short pad3;
- } state;
- struct {
+    unsigned char cmd;
+    unsigned char global;
+    unsigned short count;
+    unsigned short start;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned char cmd;
- unsigned char prim;
- unsigned short skip;
- unsigned short count;
+    unsigned short pad3;
+  } state;
+  struct {
+    unsigned char cmd;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned short start;
- } prim;
- struct {
- unsigned char cmd;
+    unsigned char prim;
+    unsigned short skip;
+    unsigned short count;
+    unsigned short start;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned char prim;
- unsigned short skip;
- unsigned short count;
- unsigned short pad3;
+  } prim;
+  struct {
+    unsigned char cmd;
+    unsigned char prim;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- } idx;
- struct {
- unsigned char cmd;
- unsigned char pad0;
+    unsigned short skip;
+    unsigned short count;
+    unsigned short pad3;
+  } idx;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned short pad1;
- unsigned int flags;
- } clear0;
- struct {
+  struct {
+    unsigned char cmd;
+    unsigned char pad0;
+    unsigned short pad1;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int mask;
- unsigned int value;
- } clear1;
+    unsigned int flags;
+  } clear0;
+  struct {
+    unsigned int mask;
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+    unsigned int value;
+  } clear1;
 };
-/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
diff --git a/libc/kernel/uapi/drm/sis_drm.h b/libc/kernel/uapi/drm/sis_drm.h
index 43789ac..5a9e868 100644
--- a/libc/kernel/uapi/drm/sis_drm.h
+++ b/libc/kernel/uapi/drm/sis_drm.h
@@ -29,30 +29,30 @@
 #define DRM_SIS_AGP_FREE 0x15
 #define DRM_SIS_FB_INIT 0x16
 #define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t)
-#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t)
+#define DRM_IOCTL_SIS_FB_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t)
 #define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t)
-#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t)
-#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t)
+#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t)
+#define DRM_IOCTL_SIS_FB_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct {
- int context;
- unsigned long offset;
- unsigned long size;
+  int context;
+  unsigned long offset;
+  unsigned long size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long free;
+  unsigned long free;
 } drm_sis_mem_t;
 typedef struct {
- unsigned long offset, size;
+  unsigned long offset, size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_sis_agp_t;
 typedef struct {
- unsigned long offset, size;
+  unsigned long offset, size;
 } drm_sis_fb_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct sis_file_private {
- struct list_head obj_list;
+  struct list_head obj_list;
 };
 #endif
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
diff --git a/libc/kernel/uapi/drm/tegra_drm.h b/libc/kernel/uapi/drm/tegra_drm.h
index 2ec83e8..e207c0c 100644
--- a/libc/kernel/uapi/drm/tegra_drm.h
+++ b/libc/kernel/uapi/drm/tegra_drm.h
@@ -23,141 +23,141 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
 struct drm_tegra_gem_create {
- __u64 size;
- __u32 flags;
+  __u64 size;
+  __u32 flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
+  __u32 handle;
 };
 struct drm_tegra_gem_mmap {
- __u32 handle;
+  __u32 handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 offset;
+  __u32 offset;
 };
 struct drm_tegra_syncpt_read {
- __u32 id;
+  __u32 id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 value;
+  __u32 value;
 };
 struct drm_tegra_syncpt_incr {
- __u32 id;
+  __u32 id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 pad;
+  __u32 pad;
 };
 struct drm_tegra_syncpt_wait {
- __u32 id;
+  __u32 id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 thresh;
- __u32 timeout;
- __u32 value;
+  __u32 thresh;
+  __u32 timeout;
+  __u32 value;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
 struct drm_tegra_open_channel {
- __u32 client;
- __u32 pad;
+  __u32 client;
+  __u32 pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 context;
+  __u64 context;
 };
 struct drm_tegra_close_channel {
- __u64 context;
+  __u64 context;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_tegra_get_syncpt {
- __u64 context;
- __u32 index;
+  __u64 context;
+  __u32 index;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 id;
+  __u32 id;
 };
 struct drm_tegra_get_syncpt_base {
- __u64 context;
+  __u64 context;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 syncpt;
- __u32 id;
+  __u32 syncpt;
+  __u32 id;
 };
 struct drm_tegra_syncpt {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 id;
- __u32 incrs;
+  __u32 id;
+  __u32 incrs;
 };
 struct drm_tegra_cmdbuf {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
- __u32 offset;
- __u32 words;
- __u32 pad;
+  __u32 handle;
+  __u32 offset;
+  __u32 words;
+  __u32 pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_tegra_reloc {
- struct {
- __u32 handle;
+  struct {
+    __u32 handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 offset;
- } cmdbuf;
- struct {
- __u32 handle;
+    __u32 offset;
+  } cmdbuf;
+  struct {
+    __u32 handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 offset;
- } target;
- __u32 shift;
- __u32 pad;
+    __u32 offset;
+  } target;
+  __u32 shift;
+  __u32 pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_tegra_waitchk {
- __u32 handle;
- __u32 offset;
+  __u32 handle;
+  __u32 offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 syncpt;
- __u32 thresh;
+  __u32 syncpt;
+  __u32 thresh;
 };
 struct drm_tegra_submit {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 context;
- __u32 num_syncpts;
- __u32 num_cmdbufs;
- __u32 num_relocs;
+  __u64 context;
+  __u32 num_syncpts;
+  __u32 num_cmdbufs;
+  __u32 num_relocs;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 num_waitchks;
- __u32 waitchk_mask;
- __u32 timeout;
- __u64 syncpts;
+  __u32 num_waitchks;
+  __u32 waitchk_mask;
+  __u32 timeout;
+  __u64 syncpts;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u64 cmdbufs;
- __u64 relocs;
- __u64 waitchks;
- __u32 fence;
+  __u64 cmdbufs;
+  __u64 relocs;
+  __u64 waitchks;
+  __u32 fence;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 reserved[5];
+  __u32 reserved[5];
 };
 #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
 #define DRM_TEGRA_GEM_TILING_MODE_TILED 1
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
 struct drm_tegra_gem_set_tiling {
- __u32 handle;
- __u32 mode;
+  __u32 handle;
+  __u32 mode;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 value;
- __u32 pad;
+  __u32 value;
+  __u32 pad;
 };
 struct drm_tegra_gem_get_tiling {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
- __u32 mode;
- __u32 value;
- __u32 pad;
+  __u32 handle;
+  __u32 mode;
+  __u32 value;
+  __u32 pad;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
 #define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
 struct drm_tegra_gem_set_flags {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
- __u32 flags;
+  __u32 handle;
+  __u32 flags;
 };
 struct drm_tegra_gem_get_flags {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 handle;
- __u32 flags;
+  __u32 handle;
+  __u32 flags;
 };
 #define DRM_TEGRA_GEM_CREATE 0x00
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
diff --git a/libc/kernel/uapi/drm/via_drm.h b/libc/kernel/uapi/drm/via_drm.h
index 5321a5d..8be086c 100644
--- a/libc/kernel/uapi/drm/via_drm.h
+++ b/libc/kernel/uapi/drm/via_drm.h
@@ -28,7 +28,7 @@
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIA_NR_XVMC_LOCKS 5
 #define VIA_MAX_CACHELINE_SIZE 64
-#define XVMCLOCKPTR(saPriv,lockNo)   ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) +   (VIA_MAX_CACHELINE_SIZE - 1)) &   ~(VIA_MAX_CACHELINE_SIZE - 1)) +   VIA_MAX_CACHELINE_SIZE*(lockNo)))
+#define XVMCLOCKPTR(saPriv,lockNo) ((volatile struct drm_hw_lock *) (((((unsigned long) (saPriv)->XvMCLockArea) + (VIA_MAX_CACHELINE_SIZE - 1)) & ~(VIA_MAX_CACHELINE_SIZE - 1)) + VIA_MAX_CACHELINE_SIZE * (lockNo)))
 #define VIA_NR_TEX_REGIONS 64
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define VIA_LOG_MIN_TEX_REGION_SIZE 16
@@ -64,20 +64,20 @@
 #define DRM_VIA_DMA_BLIT 0x0e
 #define DRM_VIA_BLIT_SYNC 0x0f
 #define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
-#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
+#define DRM_IOCTL_VIA_FREEMEM DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
 #define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
 #define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
-#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
+#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
-#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
-#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH)
-#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
+#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
+#define DRM_IOCTL_VIA_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_VIA_FLUSH)
+#define DRM_IOCTL_VIA_PCICMD DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE,   drm_via_cmdbuf_size_t)
-#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
+#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, drm_via_cmdbuf_size_t)
+#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
 #define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
 #define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -94,152 +94,152 @@
 #define VIA_MEM_MIXED 3
 #define VIA_MEM_UNKNOWN 4
 typedef struct {
- __u32 offset;
+  __u32 offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 size;
+  __u32 size;
 } drm_via_agp_t;
 typedef struct {
- __u32 offset;
+  __u32 offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 size;
+  __u32 size;
 } drm_via_fb_t;
 typedef struct {
- __u32 context;
+  __u32 context;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 type;
- __u32 size;
- unsigned long index;
- unsigned long offset;
+  __u32 type;
+  __u32 size;
+  unsigned long index;
+  unsigned long offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_via_mem_t;
 typedef struct _drm_via_init {
- enum {
- VIA_INIT_MAP = 0x01,
+  enum {
+    VIA_INIT_MAP = 0x01,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- VIA_CLEANUP_MAP = 0x02
- } func;
- unsigned long sarea_priv_offset;
- unsigned long fb_offset;
+    VIA_CLEANUP_MAP = 0x02
+  } func;
+  unsigned long sarea_priv_offset;
+  unsigned long fb_offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long mmio_offset;
- unsigned long agpAddr;
+  unsigned long mmio_offset;
+  unsigned long agpAddr;
 } drm_via_init_t;
 typedef struct _drm_via_futex {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- enum {
- VIA_FUTEX_WAIT = 0x00,
- VIA_FUTEX_WAKE = 0X01
- } func;
+  enum {
+    VIA_FUTEX_WAIT = 0x00,
+    VIA_FUTEX_WAKE = 0X01
+  } func;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 ms;
- __u32 lock;
- __u32 val;
+  __u32 ms;
+  __u32 lock;
+  __u32 val;
 } drm_via_futex_t;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 typedef struct _drm_via_dma_init {
- enum {
- VIA_INIT_DMA = 0x01,
- VIA_CLEANUP_DMA = 0x02,
+  enum {
+    VIA_INIT_DMA = 0x01,
+    VIA_CLEANUP_DMA = 0x02,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- VIA_DMA_INITIALIZED = 0x03
- } func;
- unsigned long offset;
- unsigned long size;
+    VIA_DMA_INITIALIZED = 0x03
+  } func;
+  unsigned long offset;
+  unsigned long size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long reg_pause_addr;
+  unsigned long reg_pause_addr;
 } drm_via_dma_init_t;
 typedef struct _drm_via_cmdbuffer {
- char __user *buf;
+  char __user * buf;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned long size;
+  unsigned long size;
 } drm_via_cmdbuffer_t;
 typedef struct _drm_via_tex_region {
- unsigned char next, prev;
+  unsigned char next, prev;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned char inUse;
- int age;
+  unsigned char inUse;
+  int age;
 } drm_via_tex_region_t;
 typedef struct _drm_via_sarea {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int dirty;
- unsigned int nbox;
- struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
- drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
+  unsigned int dirty;
+  unsigned int nbox;
+  struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
+  drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int texAge;
- int ctxOwner;
- int vertexPrim;
- char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
+  int texAge;
+  int ctxOwner;
+  int vertexPrim;
+  char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
- unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
- unsigned int XvMCCtxNoGrabbed;
- unsigned int pfCurrentOffset;
+  unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
+  unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
+  unsigned int XvMCCtxNoGrabbed;
+  unsigned int pfCurrentOffset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_via_sarea_t;
 typedef struct _drm_via_cmdbuf_size {
- enum {
- VIA_CMDBUF_SPACE = 0x01,
+  enum {
+    VIA_CMDBUF_SPACE = 0x01,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- VIA_CMDBUF_LAG = 0x02
- } func;
- int wait;
- __u32 size;
+    VIA_CMDBUF_LAG = 0x02
+  } func;
+  int wait;
+  __u32 size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 } drm_via_cmdbuf_size_t;
 typedef enum {
- VIA_IRQ_ABSOLUTE = 0x0,
- VIA_IRQ_RELATIVE = 0x1,
+  VIA_IRQ_ABSOLUTE = 0x0,
+  VIA_IRQ_RELATIVE = 0x1,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- VIA_IRQ_SIGNAL = 0x10000000,
- VIA_IRQ_FORCE_SEQUENCE = 0x20000000
+  VIA_IRQ_SIGNAL = 0x10000000,
+  VIA_IRQ_FORCE_SEQUENCE = 0x20000000
 } via_irq_seq_type_t;
 #define VIA_IRQ_FLAGS_MASK 0xF0000000
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum drm_via_irqs {
- drm_via_irq_hqv0 = 0,
- drm_via_irq_hqv1,
- drm_via_irq_dma0_dd,
+  drm_via_irq_hqv0 = 0,
+  drm_via_irq_hqv1,
+  drm_via_irq_dma0_dd,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_via_irq_dma0_td,
- drm_via_irq_dma1_dd,
- drm_via_irq_dma1_td,
- drm_via_irq_num
+  drm_via_irq_dma0_td,
+  drm_via_irq_dma1_dd,
+  drm_via_irq_dma1_td,
+  drm_via_irq_num
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_via_wait_irq_request {
- unsigned irq;
- via_irq_seq_type_t type;
+  unsigned irq;
+  via_irq_seq_type_t type;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 sequence;
- __u32 signal;
+  __u32 sequence;
+  __u32 signal;
 };
 typedef union drm_via_irqwait {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_via_wait_irq_request request;
- struct drm_wait_vblank_reply reply;
+  struct drm_via_wait_irq_request request;
+  struct drm_wait_vblank_reply reply;
 } drm_via_irqwait_t;
 typedef struct drm_via_blitsync {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 sync_handle;
- unsigned engine;
+  __u32 sync_handle;
+  unsigned engine;
 } drm_via_blitsync_t;
 typedef struct drm_via_dmablit {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- __u32 num_lines;
- __u32 line_length;
- __u32 fb_addr;
- __u32 fb_stride;
+  __u32 num_lines;
+  __u32 line_length;
+  __u32 fb_addr;
+  __u32 fb_stride;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- unsigned char *mem_addr;
- __u32 mem_stride;
- __u32 flags;
- int to_fb;
+  unsigned char * mem_addr;
+  __u32 mem_stride;
+  __u32 flags;
+  int to_fb;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_via_blitsync_t sync;
+  drm_via_blitsync_t sync;
 } drm_via_dmablit_t;
 struct via_file_private {
- struct list_head obj_list;
+  struct list_head obj_list;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #endif
diff --git a/libc/kernel/uapi/drm/vmwgfx_drm.h b/libc/kernel/uapi/drm/vmwgfx_drm.h
index 9d8a905..c12cdd1 100644
--- a/libc/kernel/uapi/drm/vmwgfx_drm.h
+++ b/libc/kernel/uapi/drm/vmwgfx_drm.h
@@ -69,306 +69,306 @@
 #define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
 #define DRM_VMW_PARAM_MAX_MOB_SIZE 10
 enum drm_vmw_handle_type {
- DRM_VMW_HANDLE_LEGACY = 0,
+  DRM_VMW_HANDLE_LEGACY = 0,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- DRM_VMW_HANDLE_PRIME = 1
+  DRM_VMW_HANDLE_PRIME = 1
 };
 struct drm_vmw_getparam_arg {
- uint64_t value;
+  uint64_t value;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t param;
- uint32_t pad64;
+  uint32_t param;
+  uint32_t pad64;
 };
 struct drm_vmw_context_arg {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int32_t cid;
- uint32_t pad64;
+  int32_t cid;
+  uint32_t pad64;
 };
 struct drm_vmw_surface_create_req {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t flags;
- uint32_t format;
- uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];
- uint64_t size_addr;
+  uint32_t flags;
+  uint32_t format;
+  uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];
+  uint64_t size_addr;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int32_t shareable;
- int32_t scanout;
+  int32_t shareable;
+  int32_t scanout;
 };
 struct drm_vmw_surface_arg {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int32_t sid;
- enum drm_vmw_handle_type handle_type;
+  int32_t sid;
+  enum drm_vmw_handle_type handle_type;
 };
 struct drm_vmw_size {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t width;
- uint32_t height;
- uint32_t depth;
- uint32_t pad64;
+  uint32_t width;
+  uint32_t height;
+  uint32_t depth;
+  uint32_t pad64;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 union drm_vmw_surface_create_arg {
- struct drm_vmw_surface_arg rep;
- struct drm_vmw_surface_create_req req;
+  struct drm_vmw_surface_arg rep;
+  struct drm_vmw_surface_create_req req;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 union drm_vmw_surface_reference_arg {
- struct drm_vmw_surface_create_req rep;
- struct drm_vmw_surface_arg req;
+  struct drm_vmw_surface_create_req rep;
+  struct drm_vmw_surface_arg req;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 #define DRM_VMW_EXECBUF_VERSION 1
 struct drm_vmw_execbuf_arg {
- uint64_t commands;
+  uint64_t commands;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t command_size;
- uint32_t throttle_us;
- uint64_t fence_rep;
- uint32_t version;
+  uint32_t command_size;
+  uint32_t throttle_us;
+  uint64_t fence_rep;
+  uint32_t version;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t flags;
+  uint32_t flags;
 };
 struct drm_vmw_fence_rep {
- uint32_t handle;
+  uint32_t handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t mask;
- uint32_t seqno;
- uint32_t passed_seqno;
- uint32_t pad64;
+  uint32_t mask;
+  uint32_t seqno;
+  uint32_t passed_seqno;
+  uint32_t pad64;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int32_t error;
+  int32_t error;
 };
 struct drm_vmw_alloc_dmabuf_req {
- uint32_t size;
+  uint32_t size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pad64;
+  uint32_t pad64;
 };
 struct drm_vmw_dmabuf_rep {
- uint64_t map_handle;
+  uint64_t map_handle;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t cur_gmr_id;
- uint32_t cur_gmr_offset;
- uint32_t pad64;
+  uint32_t handle;
+  uint32_t cur_gmr_id;
+  uint32_t cur_gmr_offset;
+  uint32_t pad64;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 union drm_vmw_alloc_dmabuf_arg {
- struct drm_vmw_alloc_dmabuf_req req;
- struct drm_vmw_dmabuf_rep rep;
+  struct drm_vmw_alloc_dmabuf_req req;
+  struct drm_vmw_dmabuf_rep rep;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_vmw_unref_dmabuf_arg {
- uint32_t handle;
- uint32_t pad64;
+  uint32_t handle;
+  uint32_t pad64;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_vmw_rect {
- int32_t x;
- int32_t y;
+  int32_t x;
+  int32_t y;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t w;
- uint32_t h;
+  uint32_t w;
+  uint32_t h;
 };
 struct drm_vmw_control_stream_arg {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t stream_id;
- uint32_t enabled;
- uint32_t flags;
- uint32_t color_key;
+  uint32_t stream_id;
+  uint32_t enabled;
+  uint32_t flags;
+  uint32_t color_key;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t offset;
- int32_t format;
- uint32_t size;
+  uint32_t handle;
+  uint32_t offset;
+  int32_t format;
+  uint32_t size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t width;
- uint32_t height;
- uint32_t pitch[3];
- uint32_t pad64;
+  uint32_t width;
+  uint32_t height;
+  uint32_t pitch[3];
+  uint32_t pad64;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- struct drm_vmw_rect src;
- struct drm_vmw_rect dst;
+  struct drm_vmw_rect src;
+  struct drm_vmw_rect dst;
 };
 #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
 struct drm_vmw_cursor_bypass_arg {
- uint32_t flags;
- uint32_t crtc_id;
+  uint32_t flags;
+  uint32_t crtc_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int32_t xpos;
- int32_t ypos;
- int32_t xhot;
- int32_t yhot;
+  int32_t xpos;
+  int32_t ypos;
+  int32_t xhot;
+  int32_t yhot;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_vmw_stream_arg {
- uint32_t stream_id;
- uint32_t pad64;
+  uint32_t stream_id;
+  uint32_t pad64;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_vmw_get_3d_cap_arg {
- uint64_t buffer;
- uint32_t max_size;
+  uint64_t buffer;
+  uint32_t max_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pad64;
+  uint32_t pad64;
 };
 #define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
 #define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
 struct drm_vmw_fence_wait_arg {
- uint32_t handle;
- int32_t cookie_valid;
+  uint32_t handle;
+  int32_t cookie_valid;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t kernel_cookie;
- uint64_t timeout_us;
- int32_t lazy;
- int32_t flags;
+  uint64_t kernel_cookie;
+  uint64_t timeout_us;
+  int32_t lazy;
+  int32_t flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int32_t wait_options;
- int32_t pad64;
+  int32_t wait_options;
+  int32_t pad64;
 };
 struct drm_vmw_fence_signaled_arg {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t flags;
- int32_t signaled;
- uint32_t passed_seqno;
+  uint32_t handle;
+  uint32_t flags;
+  int32_t signaled;
+  uint32_t passed_seqno;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t signaled_flags;
- uint32_t pad64;
+  uint32_t signaled_flags;
+  uint32_t pad64;
 };
 struct drm_vmw_fence_arg {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t handle;
- uint32_t pad64;
+  uint32_t handle;
+  uint32_t pad64;
 };
 #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_vmw_event_fence {
- struct drm_event base;
- uint64_t user_data;
- uint32_t tv_sec;
+  struct drm_event base;
+  uint64_t user_data;
+  uint32_t tv_sec;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t tv_usec;
+  uint32_t tv_usec;
 };
 #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
 struct drm_vmw_fence_event_arg {
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint64_t fence_rep;
- uint64_t user_data;
- uint32_t handle;
- uint32_t flags;
+  uint64_t fence_rep;
+  uint64_t user_data;
+  uint32_t handle;
+  uint32_t flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_vmw_present_arg {
- uint32_t fb_id;
- uint32_t sid;
+  uint32_t fb_id;
+  uint32_t sid;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- int32_t dest_x;
- int32_t dest_y;
- uint64_t clips_ptr;
- uint32_t num_clips;
+  int32_t dest_x;
+  int32_t dest_y;
+  uint64_t clips_ptr;
+  uint32_t num_clips;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t pad64;
+  uint32_t pad64;
 };
 struct drm_vmw_present_readback_arg {
- uint32_t fb_id;
+  uint32_t fb_id;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t num_clips;
- uint64_t clips_ptr;
- uint64_t fence_rep;
+  uint32_t num_clips;
+  uint64_t clips_ptr;
+  uint64_t fence_rep;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_vmw_update_layout_arg {
- uint32_t num_outputs;
- uint32_t pad64;
- uint64_t rects;
+  uint32_t num_outputs;
+  uint32_t pad64;
+  uint64_t rects;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 enum drm_vmw_shader_type {
- drm_vmw_shader_type_vs = 0,
- drm_vmw_shader_type_ps,
+  drm_vmw_shader_type_vs = 0,
+  drm_vmw_shader_type_ps,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_vmw_shader_type_gs
+  drm_vmw_shader_type_gs
 };
 struct drm_vmw_shader_create_arg {
- enum drm_vmw_shader_type shader_type;
+  enum drm_vmw_shader_type shader_type;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t size;
- uint32_t buffer_handle;
- uint32_t shader_handle;
- uint64_t offset;
+  uint32_t size;
+  uint32_t buffer_handle;
+  uint32_t shader_handle;
+  uint64_t offset;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_vmw_shader_arg {
- uint32_t handle;
- uint32_t pad64;
+  uint32_t handle;
+  uint32_t pad64;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 enum drm_vmw_surface_flags {
- drm_vmw_surface_flag_shareable = (1 << 0),
- drm_vmw_surface_flag_scanout = (1 << 1),
+  drm_vmw_surface_flag_shareable = (1 << 0),
+  drm_vmw_surface_flag_scanout = (1 << 1),
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_vmw_surface_flag_create_buffer = (1 << 2)
+  drm_vmw_surface_flag_create_buffer = (1 << 2)
 };
 struct drm_vmw_gb_surface_create_req {
- uint32_t svga3d_flags;
+  uint32_t svga3d_flags;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t format;
- uint32_t mip_levels;
- enum drm_vmw_surface_flags drm_surface_flags;
- uint32_t multisample_count;
+  uint32_t format;
+  uint32_t mip_levels;
+  enum drm_vmw_surface_flags drm_surface_flags;
+  uint32_t multisample_count;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t autogen_filter;
- uint32_t buffer_handle;
- uint32_t pad64;
- struct drm_vmw_size base_size;
+  uint32_t autogen_filter;
+  uint32_t buffer_handle;
+  uint32_t pad64;
+  struct drm_vmw_size base_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 };
 struct drm_vmw_gb_surface_create_rep {
- uint32_t handle;
- uint32_t backup_size;
+  uint32_t handle;
+  uint32_t backup_size;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- uint32_t buffer_handle;
- uint32_t buffer_size;
- uint64_t buffer_map_handle;
+  uint32_t buffer_handle;
+  uint32_t buffer_size;
+  uint64_t buffer_map_handle;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 union drm_vmw_gb_surface_create_arg {
- struct drm_vmw_gb_surface_create_rep rep;
- struct drm_vmw_gb_surface_create_req req;
+  struct drm_vmw_gb_surface_create_rep rep;
+  struct drm_vmw_gb_surface_create_req req;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 struct drm_vmw_gb_surface_ref_rep {
- struct drm_vmw_gb_surface_create_req creq;
- struct drm_vmw_gb_surface_create_rep crep;
+  struct drm_vmw_gb_surface_create_req creq;
+  struct drm_vmw_gb_surface_create_rep crep;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 union drm_vmw_gb_surface_reference_arg {
- struct drm_vmw_gb_surface_ref_rep rep;
- struct drm_vmw_surface_arg req;
+  struct drm_vmw_gb_surface_ref_rep rep;
+  struct drm_vmw_surface_arg req;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 enum drm_vmw_synccpu_flags {
- drm_vmw_synccpu_read = (1 << 0),
- drm_vmw_synccpu_write = (1 << 1),
- drm_vmw_synccpu_dontblock = (1 << 2),
+  drm_vmw_synccpu_read = (1 << 0),
+  drm_vmw_synccpu_write = (1 << 1),
+  drm_vmw_synccpu_dontblock = (1 << 2),
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_vmw_synccpu_allow_cs = (1 << 3)
+  drm_vmw_synccpu_allow_cs = (1 << 3)
 };
 enum drm_vmw_synccpu_op {
- drm_vmw_synccpu_grab,
+  drm_vmw_synccpu_grab,
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- drm_vmw_synccpu_release
+  drm_vmw_synccpu_release
 };
 struct drm_vmw_synccpu_arg {
- enum drm_vmw_synccpu_op op;
+  enum drm_vmw_synccpu_op op;
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
- enum drm_vmw_synccpu_flags flags;
- uint32_t handle;
- uint32_t pad64;
+  enum drm_vmw_synccpu_flags flags;
+  uint32_t handle;
+  uint32_t pad64;
 };
 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
 #endif