Unified sysroot: kill arch-specific include dirs.
<machine/asm.h> was internal use only.
<machine/fenv.h> is quite large, but can live in <bits/...>.
<machine/regdef.h> is trivially replaced by saying $x instead of x in
our assembler.
<machine/setjmp.h> is trivially inlined into <setjmp.h>.
<sgidefs.h> is unused.
Bug: N/A
Test: builds
Change-Id: Id05dbab43a2f9537486efb8f27a5ef167b055815
diff --git a/libc/include/bits/fenv_arm.h b/libc/include/bits/fenv_arm.h
new file mode 100644
index 0000000..542ddbe
--- /dev/null
+++ b/libc/include/bits/fenv_arm.h
@@ -0,0 +1,63 @@
+/*-
+ * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $
+ */
+
+/*
+ * Rewritten for Android.
+ *
+ * The ARM FPSCR is described here:
+ * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/Chdfafia.html
+ */
+
+#ifndef _BITS_FENV_ARM_H_
+#define _BITS_FENV_ARM_H_
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+typedef __uint32_t fenv_t;
+typedef __uint32_t fexcept_t;
+
+/* Exception flags. */
+#define FE_INVALID 0x01
+#define FE_DIVBYZERO 0x02
+#define FE_OVERFLOW 0x04
+#define FE_UNDERFLOW 0x08
+#define FE_INEXACT 0x10
+#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
+ FE_OVERFLOW | FE_UNDERFLOW)
+
+/* Rounding modes. */
+#define FE_TONEAREST 0x0
+#define FE_UPWARD 0x1
+#define FE_DOWNWARD 0x2
+#define FE_TOWARDZERO 0x3
+
+__END_DECLS
+
+#endif
diff --git a/libc/include/bits/fenv_arm64.h b/libc/include/bits/fenv_arm64.h
new file mode 100644
index 0000000..67f0fb4
--- /dev/null
+++ b/libc/include/bits/fenv_arm64.h
@@ -0,0 +1,102 @@
+/*-
+ * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $
+ */
+
+/*
+ * In ARMv8, AArch64 state, floating-point operation is controlled by:
+ *
+ * * FPCR - 32Bit Floating-Point Control Register:
+ * * [31:27] - Reserved, Res0;
+ * * [26] - AHP, Alternative half-precision control bit;
+ * * [25] - DN, Default NaN mode control bit;
+ * * [24] - FZ, Flush-to-zero mode control bit;
+ * * [23:22] - RMode, Rounding Mode control field:
+ * * 00 - Round to Nearest (RN) mode;
+ * * 01 - Round towards Plus Infinity (RP) mode;
+ * * 10 - Round towards Minus Infinity (RM) mode;
+ * * 11 - Round towards Zero (RZ) mode.
+ * * [21:20] - Stride, ignored during AArch64 execution;
+ * * [19] - Reserved, Res0;
+ * * [18:16] - Len, ignored during AArch64 execution;
+ * * [15] - IDE, Input Denormal exception trap;
+ * * [14:13] - Reserved, Res0;
+ * * [12] - IXE, Inexact exception trap;
+ * * [11] - UFE, Underflow exception trap;
+ * * [10] - OFE, Overflow exception trap;
+ * * [9] - DZE, Division by Zero exception;
+ * * [8] - IOE, Invalid Operation exception;
+ * * [7:0] - Reserved, Res0.
+ *
+ * * FPSR - 32Bit Floating-Point Status Register:
+ * * [31] - N, Negative condition flag for AArch32 (AArch64 sets PSTATE.N);
+ * * [30] - Z, Zero condition flag for AArch32 (AArch64 sets PSTATE.Z);
+ * * [29] - C, Carry conditon flag for AArch32 (AArch64 sets PSTATE.C);
+ * * [28] - V, Overflow conditon flag for AArch32 (AArch64 sets PSTATE.V);
+ * * [27] - QC, Cumulative saturation bit, Advanced SIMD only;
+ * * [26:8] - Reserved, Res0;
+ * * [7] - IDC, Input Denormal cumulative exception;
+ * * [6:5] - Reserved, Res0;
+ * * [4] - IXC, Inexact cumulative exception;
+ * * [3] - UFC, Underflow cumulative exception;
+ * * [2] - OFC, Overflow cumulative exception;
+ * * [1] - DZC, Division by Zero cumulative exception;
+ * * [0] - IOC, Invalid Operation cumulative exception.
+ */
+
+#ifndef _BITS_FENV_ARM64_H_
+#define _BITS_FENV_ARM64_H_
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+typedef struct {
+ __uint32_t __control; /* FPCR, Floating-point Control Register */
+ __uint32_t __status; /* FPSR, Floating-point Status Register */
+} fenv_t;
+
+typedef __uint32_t fexcept_t;
+
+/* Exception flags. */
+#define FE_INVALID 0x01
+#define FE_DIVBYZERO 0x02
+#define FE_OVERFLOW 0x04
+#define FE_UNDERFLOW 0x08
+#define FE_INEXACT 0x10
+#define FE_DENORMAL 0x80
+#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
+ FE_OVERFLOW | FE_UNDERFLOW | FE_DENORMAL)
+
+/* Rounding modes. */
+#define FE_TONEAREST 0x0
+#define FE_UPWARD 0x1
+#define FE_DOWNWARD 0x2
+#define FE_TOWARDZERO 0x3
+
+__END_DECLS
+
+#endif
diff --git a/libc/include/bits/fenv_mips.h b/libc/include/bits/fenv_mips.h
new file mode 100644
index 0000000..9298e86
--- /dev/null
+++ b/libc/include/bits/fenv_mips.h
@@ -0,0 +1,98 @@
+/*-
+ * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $
+ */
+
+/*
+ Rewritten for Android.
+*/
+
+/* MIPS FPU floating point control register bits.
+ *
+ * 31-25 -> floating point conditions code bits set by FP compare
+ * instructions
+ * 24 -> flush denormalized results to zero instead of
+ * causing unimplemented operation exception.
+ * 23 -> Condition bit
+ * 22 -> In conjunction with FS detects denormalized
+ * operands and replaces them internally with 0.
+ * 21 -> In conjunction with FS forces denormalized operands
+ * to the closest normalized value.
+ * 20-18 -> reserved (read as 0, write with 0)
+ * 17 -> cause bit for unimplemented operation
+ * 16 -> cause bit for invalid exception
+ * 15 -> cause bit for division by zero exception
+ * 14 -> cause bit for overflow exception
+ * 13 -> cause bit for underflow exception
+ * 12 -> cause bit for inexact exception
+ * 11 -> enable exception for invalid exception
+ * 10 -> enable exception for division by zero exception
+ * 9 -> enable exception for overflow exception
+ * 8 -> enable exception for underflow exception
+ * 7 -> enable exception for inexact exception
+ * 6 -> flag invalid exception
+ * 5 -> flag division by zero exception
+ * 4 -> flag overflow exception
+ * 3 -> flag underflow exception
+ * 2 -> flag inexact exception
+ * 1-0 -> rounding control
+ *
+ *
+ * Rounding Control:
+ * 00 - rounding to nearest (RN)
+ * 01 - rounding toward zero (RZ)
+ * 10 - rounding (up) toward plus infinity (RP)
+ * 11 - rounding (down)toward minus infinity (RM)
+ */
+
+#ifndef _BITS_FENV_MIPS_H_
+#define _BITS_FENV_MIPS_H_
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+typedef __uint32_t fenv_t;
+typedef __uint32_t fexcept_t;
+
+/* Exception flags */
+#define FE_INVALID 0x40
+#define FE_DIVBYZERO 0x20
+#define FE_OVERFLOW 0x10
+#define FE_UNDERFLOW 0x08
+#define FE_INEXACT 0x04
+#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
+ FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
+
+/* Rounding modes */
+#define FE_TONEAREST 0x0000
+#define FE_TOWARDZERO 0x0001
+#define FE_UPWARD 0x0002
+#define FE_DOWNWARD 0x0003
+
+__END_DECLS
+
+#endif
diff --git a/libc/include/bits/fenv_x86.h b/libc/include/bits/fenv_x86.h
new file mode 100644
index 0000000..75b109b
--- /dev/null
+++ b/libc/include/bits/fenv_x86.h
@@ -0,0 +1,69 @@
+/*-
+ * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/lib/msun/i387/fenv.h,v 1.4 2005/03/17 22:21:46 das Exp $
+ */
+
+#ifndef _BITS_FENV_X86_H_
+#define _BITS_FENV_X86_H_
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+/*
+ * To preserve binary compatibility with FreeBSD 5.3, we pack the
+ * mxcsr into some reserved fields, rather than changing sizeof(fenv_t).
+ */
+typedef struct {
+ __uint16_t __control;
+ __uint16_t __mxcsr_hi;
+ __uint16_t __status;
+ __uint16_t __mxcsr_lo;
+ __uint32_t __tag;
+ char __other[16];
+} fenv_t;
+
+typedef __uint16_t fexcept_t;
+
+/* Exception flags */
+#define FE_INVALID 0x01
+#define FE_DENORMAL 0x02
+#define FE_DIVBYZERO 0x04
+#define FE_OVERFLOW 0x08
+#define FE_UNDERFLOW 0x10
+#define FE_INEXACT 0x20
+#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_DENORMAL | FE_INEXACT | \
+ FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
+
+/* Rounding modes */
+#define FE_TONEAREST 0x0000
+#define FE_DOWNWARD 0x0400
+#define FE_UPWARD 0x0800
+#define FE_TOWARDZERO 0x0c00
+
+__END_DECLS
+
+#endif
diff --git a/libc/include/bits/fenv_x86_64.h b/libc/include/bits/fenv_x86_64.h
new file mode 100644
index 0000000..006d19e
--- /dev/null
+++ b/libc/include/bits/fenv_x86_64.h
@@ -0,0 +1,95 @@
+/*-
+ * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _BITS_FENV_X86_64_H_
+#define _BITS_FENV_X86_64_H_
+
+#include <sys/types.h>
+
+__BEGIN_DECLS
+
+/*
+ * Each symbol representing a floating point exception expands to an integer
+ * constant expression with values, such that bitwise-inclusive ORs of _all
+ * combinations_ of the constants result in distinct values.
+ *
+ * We use such values that allow direct bitwise operations on FPU/SSE registers.
+ */
+#define FE_INVALID 0x01
+#define FE_DENORMAL 0x02
+#define FE_DIVBYZERO 0x04
+#define FE_OVERFLOW 0x08
+#define FE_UNDERFLOW 0x10
+#define FE_INEXACT 0x20
+
+/*
+ * The following symbol is simply the bitwise-inclusive OR of all floating-point
+ * exception constants defined above.
+ */
+#define FE_ALL_EXCEPT (FE_INVALID | FE_DENORMAL | FE_DIVBYZERO | \
+ FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT)
+
+/*
+ * Each symbol representing the rounding direction, expands to an integer
+ * constant expression whose value is distinct non-negative value.
+ *
+ * We use such values that allow direct bitwise operations on FPU/SSE registers.
+ */
+#define FE_TONEAREST 0x000
+#define FE_DOWNWARD 0x400
+#define FE_UPWARD 0x800
+#define FE_TOWARDZERO 0xc00
+
+/*
+ * fenv_t represents the entire floating-point environment.
+ */
+typedef struct {
+ struct {
+ __uint32_t __control; /* Control word register */
+ __uint32_t __status; /* Status word register */
+ __uint32_t __tag; /* Tag word register */
+ __uint32_t __others[4]; /* EIP, Pointer Selector, etc */
+ } __x87;
+ __uint32_t __mxcsr; /* Control, status register */
+} fenv_t;
+
+/*
+ * fexcept_t represents the floating-point status flags collectively, including
+ * any status the implementation associates with the flags.
+ *
+ * A floating-point status flag is a system variable whose value is set (but
+ * never cleared) when a floating-point exception is raised, which occurs as a
+ * side effect of exceptional floating-point arithmetic to provide auxiliary
+ * information.
+ *
+ * A floating-point control mode is a system variable whose value may be set by
+ * the user to affect the subsequent behavior of floating-point arithmetic.
+ */
+typedef __uint32_t fexcept_t;
+
+__END_DECLS
+
+#endif
diff --git a/libc/include/fenv.h b/libc/include/fenv.h
index ae35ae3..4276e87 100644
--- a/libc/include/fenv.h
+++ b/libc/include/fenv.h
@@ -31,7 +31,18 @@
#define _FENV_H_
#include <sys/cdefs.h>
-#include <machine/fenv.h>
+
+#if defined(__aarch64__)
+#include <bits/fenv_arm64.h>
+#elif defined(__arm__)
+#include <bits/fenv_arm.h>
+#elif defined(__i386__)
+#include <bits/fenv_x86.h>
+#elif defined(__mips__)
+#include <bits/fenv_mips.h>
+#elif defined(__x86_64__)
+#include <bits/fenv_x86_64.h>
+#endif
__BEGIN_DECLS
diff --git a/libc/include/setjmp.h b/libc/include/setjmp.h
index 12a3083..d44946f 100644
--- a/libc/include/setjmp.h
+++ b/libc/include/setjmp.h
@@ -41,11 +41,28 @@
#define _SETJMP_H_
#include <sys/cdefs.h>
-#include <machine/setjmp.h>
+
+#if defined(__aarch64__)
+#define _JBLEN 32
+#elif defined(__arm__)
+#define _JBLEN 64
+#elif defined(__i386__)
+#define _JBLEN 10
+#elif defined(__mips__)
+ #if defined(__LP64__)
+ #define _JBLEN 25
+ #else
+ #define _JBLEN 157
+ #endif
+#elif defined(__x86_64__)
+#define _JBLEN 11
+#endif
typedef long sigjmp_buf[_JBLEN + 1];
typedef long jmp_buf[_JBLEN];
+#undef _JBLEN
+
__BEGIN_DECLS
int _setjmp(jmp_buf __env);