Clean up trailing whitespace in the kernel headers.
And fix the scripts so they stop letting trailing whitespace through.
Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
diff --git a/libc/kernel/arch-x86/asm/msr-index.h b/libc/kernel/arch-x86/asm/msr-index.h
index 2336f82..10b2726 100644
--- a/libc/kernel/arch-x86/asm/msr-index.h
+++ b/libc/kernel/arch-x86/asm/msr-index.h
@@ -18,21 +18,21 @@
****************************************************************************/
#ifndef __ASM_MSR_INDEX_H
#define __ASM_MSR_INDEX_H
-#define MSR_EFER 0xc0000080
-#define MSR_STAR 0xc0000081
+#define MSR_EFER 0xc0000080
+#define MSR_STAR 0xc0000081
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MSR_LSTAR 0xc0000082
-#define MSR_CSTAR 0xc0000083
-#define MSR_SYSCALL_MASK 0xc0000084
-#define MSR_FS_BASE 0xc0000100
+#define MSR_LSTAR 0xc0000082
+#define MSR_CSTAR 0xc0000083
+#define MSR_SYSCALL_MASK 0xc0000084
+#define MSR_FS_BASE 0xc0000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define MSR_GS_BASE 0xc0000101
-#define MSR_KERNEL_GS_BASE 0xc0000102
-#define _EFER_SCE 0
-#define _EFER_LME 8
+#define MSR_GS_BASE 0xc0000101
+#define MSR_KERNEL_GS_BASE 0xc0000102
+#define _EFER_SCE 0
+#define _EFER_LME 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define _EFER_LMA 10
-#define _EFER_NX 11
+#define _EFER_LMA 10
+#define _EFER_NX 11
#define EFER_SCE (1<<_EFER_SCE)
#define EFER_LME (1<<_EFER_LME)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -107,9 +107,9 @@
#define MSR_K8_HWCR 0xc0010015
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_K8_ENABLE_C1E 0xc0010055
-#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000
-#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000
-#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818
+#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000
+#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000
+#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_K7_EVNTSEL0 0xc0010000
#define MSR_K7_PERFCTR0 0xc0010004
@@ -294,7 +294,7 @@
#define MSR_P4_SAAT_ESCR0 0x000003ae
#define MSR_P4_SAAT_ESCR1 0x000003af
#define MSR_P4_SSU_ESCR0 0x000003be
-#define MSR_P4_SSU_ESCR1 0x000003bf
+#define MSR_P4_SSU_ESCR1 0x000003bf
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_P4_TBPU_ESCR0 0x000003c2
#define MSR_P4_TBPU_ESCR1 0x000003c3