Clean up trailing whitespace in the kernel headers.
And fix the scripts so they stop letting trailing whitespace through.
Change-Id: Ie109fbe1f63321e565ba0fa60fee8e9cf3a61cfc
diff --git a/libc/kernel/arch-mips/asm/sn/sn0/addrs.h b/libc/kernel/arch-mips/asm/sn/sn0/addrs.h
index 5c056ed..8e29419 100644
--- a/libc/kernel/arch-mips/asm/sn/sn0/addrs.h
+++ b/libc/kernel/arch-mips/asm/sn/sn0/addrs.h
@@ -119,15 +119,15 @@
#define IO6DPROM_SIZE 0x200000
#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
-#define IP27PROM_INT_LAUNCH 10
+#define IP27PROM_INT_LAUNCH 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define IP27PROM_INT_NETUART 12
+#define IP27PROM_INT_NETUART 12
#endif
#define IP27PROM_ELSC_SHFT 10
#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FREEMEM_BASE PHYS_TO_K0(0x2000000)
-#define IO6PROM_STACK_SHFT 14
+#define IO6PROM_STACK_SHFT 14
#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT)
#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@@ -142,11 +142,11 @@
#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
-#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0)
-#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0)
-#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1)
+#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0)
+#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0)
+#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define KL_I2C_REG MD_UREG0_0
+#define KL_I2C_REG MD_UREG0_0
#ifndef __ASSEMBLY__
#ifdef HUB_ERR_STS_WAR
#define CACHE_ERR_EFRAME 0x480
@@ -156,7 +156,7 @@
#endif
#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
-#define CACHE_ERR_SP_PTR (0x1000 - 32)
+#define CACHE_ERR_SP_PTR (0x1000 - 32)
#define CACHE_ERR_IBASE_PTR (0x1000 - 40)
#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)